Multi-protocol I/O infrastructure for a flexible storage platform

US10776299B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10776299-B2
Application numberUS-201916433838-A
CountryUS
Kind codeB2
Filing dateJun 6, 2019
Priority dateMay 8, 2015
Publication dateSep 15, 2020
Grant dateSep 15, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage system, comprising: a storage motherboard, comprising: a first storage interface connector for connecting to a storage device; a first adapter connector; and a connector for connecting to a host; a first storage adapter circuit comprising a first motherboard connector compatible with the first adapter connector, and being configured to support, at the first motherboard connector: a first storage interface for communicating with the storage device; and a host interface for communicating with the host; and a second storage adapter circuit comprising a first motherboard connector compatible with the first adapter connector, and being configured to support, at the first motherboard connector: a first storage interface for communicating with the storage device; and a host interface for communicating with the host, the first storage interface of the first storage adapter circuit being different from the first storage interface of the second storage adapter circuit. 2. The system of claim 1 , wherein the first storage adapter circuit comprises a routing circuit. 3. The system of claim 2 , wherein the first storage adapter circuit further comprises a protocol translation circuit. 4. The system of claim 1 , wherein the storage motherboard further comprises: a second storage interface connector; and a second adapter connector, the system further comprising a third storage adapter circuit comprising a first motherboard connector compatible with the first adapter connector and with the second adapter connector, and being configured to support, at the first motherboard connector: a first storage interface; and a host interface, the first storage interface of the third storage adapter circuit being different from the first storage interface of the second storage adapter circuit. 5. The system of claim 1 , wherein the first storage adapter circuit is further configured to provide a second storage interface at the first motherboard connector of the first storage adapter circuit, the second storage interface being the same as the first storage interface of the first storage adapter circuit. 6. The system of claim 1 , wherein the first storage adapter circuit is further configured to provide a second storage interface at the first motherboard connector of the first storage adapter circuit, the second storage interface being different from the first storage interface of the first storage adapter circuit. 7. The system of claim 6 , wherein the first storage interface of the first storage adapter circuit comprises a SATA interface and the second storage interface comprises a SAS interface. 8. The system of claim 1 , wherein the host interface of the first storage adapter circuit comprises a PCIe interface, and the first storage interface of the first storage adapter circuit comprises an interface selected from the group consisting of SATA, SAS, FibreChannel, NVMe, Ethernet, and USB. 9. The system of claim 1 , wherein the host interface of the first storage adapter circuit comprises a PCIe interface, and the first storage interface of the first storage adapter circuit comprises a PCIe interface. 10. The system of claim 1 , wherein the host interface of the first storage adapter circuit comprises a SAS interface, and the first storage interface of the first storage adapter circuit comprises a SAS interface. 11. The system of claim 1 , wherein the first storage interface connector is compatible with at least two different storage interfaces. 12. The system of claim 11 , wherein the first storage interface connector comprises an SFF8639 connector. 13. A storage system, comprising: a storage motherboard, comprising: a first storage interface connector for connecting to a storage device; a first adapter connector; and a connector for connecting to a host; a first storage adapter circuit comprising: a first motherboard connector compatible with the first adapter connector, and a first storage connector, the first storage adapter circuit supporting: a first storage interface, for communicating with the storage device, at the first storage connector of the first storage adapter circuit; and a host interface, for communicating with the host, at the first motherboard connector of the first storage adapter circuit; and a second storage adapter circuit comprising: a first motherboard connector compatible with the first adapter connector, and a first storage connector, the second storage adapter circuit supporting: a first storage interface, for communicating with the storage device, at the first storage connector of the second storage adapter circuit; and a host interface, for communicating with the host, at the first motherboard connector of the second storage adapter circuit, the first storage interface of the first storage adapter circuit being different from the first storage interface of the second storage adapter circuit. 14. The system of claim 13 , further comprising a mass storage device connected to the first storage connector of the first storage adapter circuit by a data path comprising a portion selected from the group consisting of a cable, a plurality of printed circuit board traces, and a wireless link. 15. The system of claim 14 , wherein the first motherboard connector of the first storage adapter circuit comprises a PCIe connector, and the host interface of the first storage adapter circuit is PCIe. 16. The system of claim 13 , wherein the storage motherboard further comprises: a second storage interface connector; and a second adapter connector, the system further comprising a third storage adapter circuit comprising: a first motherboard connector compatible with the first adapter connector and with the second adapter connector, and a first storage connector, the third storage adapter circuit supporting: a first storage interface at the first storage connector of the third storage adapter circuit supporting; and a host interface at the first motherboard connector of the third storage adapter circuit supporting, the first storage interface of the third storage adapter circuit being different from the first storage interface of the second storage adapter circuit. 17. A computing system, comprising: a rack tray for a 19-inch rack, the rack tray comprising: a host motherboard comprising a CPU and memory; a storage motherboard, comprising: a first storage interface connector for connecting to a storage device; a first adapter connector; and a connector for connecting to a host; a first storage adapter circuit comprising a first motherboard connector compatible with the first adapter connector, and being configured to support, at the first motherboard connector: a first storage interface for communicating with the storage device; and a host interface for communicating with the host; and a second storage adapter circuit comprising a first motherboard connector compatible with the first adapter connector, and being configured to support, at the first motherboard connector: a first storage interface for communicating with the storage device; and a host interface for communicating with the host, the first storage interface of the first storage adapter circuit being different from the first storage interface of the second storage adapter circuit. 18. The system of claim 17 , wherein the storage motherboard further comprises: a second storage interface connector; and a second adapter connector, the system further comprising a third storage adapt

Assignees

Inventors

Classifications

  • Serial ATA [SATA] · CPC title

  • Serial attached SCSI [SAS] · CPC title

  • PCI express · CPC title

  • Device-to-bus coupling · CPC title

  • G06F13/387Primary

    for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10776299B2 cover?
A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit ma…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/387. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 15 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).