Transistor with recessed cross couple for gate contact over active region integration

Patent metadata

Field	Value
Publication number	US-10770388-B2
Application number	US-201816009200-A
Country	US
Kind code	B2
Filing date	Jun 15, 2018
Priority date	Jun 15, 2018
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor structure including a substrate having a first region and a second region;
a first source/drain disposed on the substrate in the first region;
an interlevel dielectric (ILD) disposed on the source/drain;
a first gate disposed on the substrate;
a first spacer disposed between the first source/drain and the first gate;
a first contact trench within the ILD extending to the first source/drain;
a first trench contact within the first contact trench;
a first source/drain contact trench extending to the first trench contact;
a cross couple contact trench within the ILD; and
a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact, the cross couple contact coupling the first source/drain and the first gate such that the cross couple contact is substantially connected to a singular surface of the first source/drain.

2. The apparatus of claim 1 , further comprising:
a first cap disposed on the first gate.

3. The apparatus of claim 1 , further comprising:
an ILD fill upon the semiconductor structure; and
a first metallization layer within the ILD fill of the first region, wherein the first metallization layer is electrically isolated from the cross couple contact.

4. The apparatus of claim 1 , further comprising:
a second source/drain disposed on the substrate in the second region;
a second contact trench within the ILD extending to the second source/drain; and
a second trench contact within the second contact trench such that the second trench contact is substantially connected to a singular surface of the second source/drain.

5. The apparatus of claim 1 , further comprising:
an anti-reflective coating material layer disposed over the semiconductor structure.

6. The apparatus of claim 1 , further comprising:
an ILD fill material disposed over the semiconductor structure.

7. The apparatus of claim 1 , further comprising:
a first metallization layer deposed within the ILD, wherein the first metallization layer is electrically isolated from the cross couple contact.

8. The apparatus of claim 1 , further comprising:
a second contact trench within the ILD extending to a second source/drain of the second region.

9. The apparatus of claim 8 , further comprising:
a second trench contact within the second contact trench.

Assignees

• IBM

Inventors

• Xie Ruilong
• Basker Veeraraghavan S
• Cheng Kangguo
• Zeng Jia
• Woo Youngtag
• Kumar Mahender
• Bouche Guillaume

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title