Semiconductor device with a gate contact positioned above the active region

Patent metadata

Field	Value
Publication number	US-9735242-B2
Application number	US-201514887927-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Oct 20, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

First claim

What is claimed:

1. A transistor device, comprising:
a gate structure;
an active region of a semiconducting substrate surrounded by an isolation region;
source/drain regions disposed on opposing sides of said gate structure, wherein a gate width direction is defined in a direction extending between said source/drain regions and a gate length direction is defined in a direction perpendicular to said gate width direction along an axial length of said gate structure;
a stepped conductive source/drain contact structure formed above and contacting one of said source/drain regions and having a first upper surface with a first height and a second upper surface with a second height greater than said first height, wherein said stepped conductive source/drain contact structure has a stepped configuration when viewed in cross-sectional view taken along through said stepped conductive source/drain contact structure in a direction corresponding to said gate width direction;
a non-conductive structure positioned above and contacting said first upper surface and having a third upper surface coplanar with said second upper surface;
a layer of insulating material positioned above said gate structure, said stepped conductive source/drain contact structure and said non-conductive structure;
a conductive gate contact disposed in said layer of insulating material and being conductively coupled to said gate structure, wherein, in a plan view of said transistor device, said non-conductive structure is disposed on left and right sides of said conductive gate contact; and
a source/drain contact disposed in said layer of insulating material and contacting said second upper surface of said source/drain contact structure.

2. The device of claim 1 , wherein an entirety of said conductive gate contact is positioned vertically above said active region.

3. The device of claim 1 , wherein said stepped conductive source/drain contact structure has an overall axial length in said gate width direction and a portion of said stepped conductive source/drain contact structure having said first height has an axial length that is approximately 5-80% of said overall axial length of said stepped conductive source/drain contact structure.

4. The device of claim 1 , wherein said first height is approximately 20-70% of said second height.

5. The device of claim 1 , wherein said transistor device further comprises:
a silicon nitride sidewall spacer positioned adjacent said gate structure; and
a T-shaped gate cap layer comprising silicon dioxide positioned above said gate structure and above an upper surface of said silicon nitride sidewall spacer, wherein said non-conductive structure comprises a silicon nitride material, and said T-shaped gate cap layer has a horizontal portion disposed above said upper surface of said silicon nitride sidewall spacer and a vertical portion extending down from said horizontal portion toward said gate structure.

6. The device of claim 1 , wherein said stepped conductive source/drain contact structure comprises a metal silicide material and a conductive metal positioned above said metal silicide material.

7. A transistor device, comprising:
a gate structure;
an active region of a semiconducting substrate surrounded by an isolation region;
source/drain regions disposed on opposing sides of said gate structure, wherein a gate width direction is defined in a direction extending between said source/drain regions and a gate length direction is defined in a direction perpendicular to said gate width direction along an axial length of said gate structure;
a stepped conductive source/drain contact structure formed above and contacting one said source/drain regions and having a first upper surface with a first height and a second upper surface with a second height greater than said first height, wherein said stepped conductive source/drain contact structure has a stepped configuration when viewed in cross-sectional view taken along through said stepped conductive source/drain contact structure in a direction corresponding to said gate width direction;
a non-conductive structure positioned above and contacting said first upper surface and having a third upper surface coplanar with said second upper surface;
a sidewall spacer positioned adjacent said gate structure;
a T-shaped gate cap layer positioned above said gate structure and on and in contact with an upper surface of said sidewall spacer, wherein said T-shaped gate cap layer has a horizontal portion disposed above said upper surface of said sidewall spacer and a vertical portion extending down from said horizontal portion toward said gate structure;
a layer of insulating material positioned above said T-shaped gate cap layer, said stepped conductive source/drain contact structure and said non-conductive structure;
a conductive gate contact disposed in said layer of insulating material and said T-shaped cap layer and being conductively coupled to said gate structure, wherein, in a plan view of said transistor device, said non-conductive structure is disposed on left and right sides of said conductive gate contact; and
a source/drain contact disposed in said layer of insulating material and contacting said second upper surface of said source/drain contact structure.

8. The device of claim 7 , wherein said stepped conductive source/drain contact structure has an overall axial length in said gate width direction and a portion of said stepped conductive source/drain contact structure having said first height has an axial length that is approximately 5-80% of said overall axial length of said stepped conductive source/drain contact structure.

9. The device of claim 7 , wherein said first height is approximately 20-70% of said second height.

10. The device of claim 7 , wherein said sidewall spacer comprises silicon nitride, said T-shaped gate cap layer comprises silicon dioxide, said layer of insulating material comprises silicon dioxide and said non-conductive structure comprises silicon nitride material.

11. A transistor device, comprising:
a gate structure;
an active region of a semiconducting substrate surrounded by an isolation region;
source/drain regions disposed on opposing sides of said gate structure, wherein a gate width direction is defined in a direction extending between said source/drain regions and a gate length direction is defined in a direction perpendicular to said gate width direction along an axial length of said gate structure;
a stepped conductive source/drain contact structure formed above and contacting said source/drain regions and having a first upper surface with a first height and a second upper surface with a second height greater than said first height, wherein said stepped conductive source/drain contact structure has a stepped configuration when viewed in cross-sectional view taken along through said stepped conductive source/drain contact structure in a direction corresponding to said gate width direction;
a non-conductive structure positioned above and contacting said first upper surface and having a third upper surface coplanar with said second upper surface;
a silicon nitride sidewall spacer positioned adjacent said gate structure;
a silicon dioxide T-shaped gate cap layer positioned above said gate structure and on and in contact with an upper surface of said silicon nitride sidewall spacer, wherein said silicon dioxide T-shaped gate cap layer has a horizontal portion disposed above said upper surface of said silicon nitride sidewall spacer and a vertical portion extending down from said horizontal portion toward said gate structure;
a layer of silicon dioxide positioned above said silicon dioxide T-shaped gate

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Sung Min Gyu
• Kim Hoon

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic