Methods of forming a gate contact above an active region of a semiconductor device

Patent metadata

Field	Value
Publication number	US-9780178-B2
Application number	US-201514731960-A
Country	US
Kind code	B2
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

First claim

What is claimed:

1. A method of forming a gate contact for a gate structure of a transistor device formed above an active region of a semiconducting substrate surrounded by an isolation region, said gate structure comprising a gate electrode, a gate cap layer and a sidewall spacer, the method comprising:
forming said gate structure above at least said active region;
forming a layer of insulating material above said gate structure;
forming a gate contact opening in said layer of insulating material, wherein said gate contact opening is positioned at least partially vertically above said active region, said gate contact opening exposing a portion of at least said gate cap layer, said gate contact opening having exposed sidewalls that extend upward through said layer of insulating material relative to said exposed portion of said gate cap layer;
performing at least one etching process through said gate contact opening to remove said exposed portion of said gate cap layer and recess said sidewall spacer so as to thereby define a spacer cavity positioned above said recessed sidewall spacer and expose at least an upper surface of said gate electrode within said gate contact opening;
performing at least one process operation to fill said spacer cavity with an insulating material while leaving said upper surface of said gate electrode exposed; and
forming a conductive gate contact in said gate contact opening that is conductively coupled to said exposed upper surface of said gate electrode, wherein said gate contact is positioned at least partially vertically above said active region.

2. The method of claim 1 , wherein forming said gate contact opening comprises forming said gate contact opening such that the entire gate contact opening is positioned above said active region.

3. The method of claim 1 , wherein performing said at least one etching process through said gate contact opening to remove said gate cap layer and recess said sidewall spacer comprises performing a single etching process through said gate contact opening to remove said gate cap layer and recess said sidewall spacer.

4. The method of claim 1 , wherein performing said at least one process operation to fill said spacer cavity with an insulating material comprises:
performing a conformal deposition process to form a conformal layer of insulating material in said gate contact opening so as to overfill said spacer cavity and to line said exposed sidewalls of said gate contact opening; and
performing an etching process so as to remove portions of said conformal layer of insulating material while a remaining portion of said conformal layer of insulating material is positioned in said spacer cavity above said recessed sidewall spacer.

5. The method of claim 4 , wherein performing said etching process so as to remove portions of said conformal layer of insulating material comprises performing an isotropic etching process so as to remove portions of said conformal layer of insulating material.

6. The method of claim 1 , wherein said gate cap layer and said sidewall spacer are comprised of silicon nitride.

7. The method of claim 1 , wherein said transistor device is one of a FinFET transistor device or a planar transistor device.

8. The method of claim 1 , wherein said gate electrode is comprised of at least one layer of metal.

9. The method of claim 1 , wherein said gate contact is comprised of tungsten or copper.

10. A method of forming a gate contact for a gate structure of a transistor device formed above an active region of a semiconducting substrate surrounded by an isolation region, said gate structure comprising a gate electrode, a gate cap layer and a sidewall spacer, the method comprising:
forming said gate structure above at least said active region;
forming a layer of insulating material above said gate structure;
forming a patterned etch mask above said layer of insulating material;
performing an etching process through said patterned etch mask to form a gate contact opening that extends through said layer of insulating material, wherein the entire gate contact opening is positioned vertically above said active region, said gate contact opening exposing a portion of at least said gate cap layer and sidewall surfaces of said layer of insulating material;
performing at least one etching process through said gate contact opening to remove said exposed portion of said gate cap layer and recess said sidewall spacer so as to thereby define a spacer cavity positioned above said recessed sidewall spacer and expose at least an upper surface of said gate electrode within said gate contact opening;
performing a conformal deposition process to form a conformal layer of insulating material in said gate contact opening so as to overfill said spacer cavity, to cover said exposed upper surface of said gate electrode, and to line said exposed sidewall surfaces of said layer of insulating material;
performing an etching process so as to remove portions of said conformal layer of insulating material and expose at least said upper surface of said gate electrode while a remaining portion of said conformal layer of insulating material is positioned in said spacer cavity above said recessed sidewall spacer; and
forming a conductive gate contact in said gate contact opening that is conductively coupled to said exposed upper surface of said gate electrode, wherein the entire conductive gate contact is positioned vertically above said active region.

11. The method of claim 10 , wherein performing said at least one etching process through said gate contact opening to remove said gate cap layer and recess said sidewall spacer comprises performing a single etching process through said gate contact opening to remove said gate cap layer and recess said sidewall spacer.

12. The method of claim 10 , wherein performing said etching process so as to remove portions of said conformal layer of insulating material comprises performing an isotropic etching process so as to remove portions of said conformal layer of insulating material.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Labonte Andre
• Knorr Andreas

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/7851

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic