Matrix normal/transpose read and a reconfigurable data processor including same

Patent metadata

Field	Value
Publication number	US-10768899-B2
Application number	US-201916260548-A
Country	US
Kind code	B2
Filing date	Jan 29, 2019
Priority date	Jan 29, 2019
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.

First claim

The invention claimed is:

1. A configurable circuit, comprising:
a memory array;
logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data;
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix; and
normal read logic to output vectors of a normal read of the matrix;
wherein the transpose read logic and the normal read logic are operable on the memory array to output in parallel respective vectors in transposed and normal orders.

2. The circuit of claim 1 , wherein the memory array includes a first read port and a second read port, and the normal read logic is operably coupled to the first read port and the transpose read logic is operably coupled to the second read port.

3. A configurable circuit, comprising:
a memory array;
logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data;
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix; and
normal read logic to output vectors of a normal read of the matrix;
wherein the memory array includes a plurality of slots, where slots in the plurality of slots include have a slot width (number of columns) equal to a multiple M greater than 1 of the data width.

4. The circuit of claim 3 , wherein the logic to write comprises logic to organize sets of M rows of the matrix in the memory into a plurality of rows of atoms of M by M elements, atoms in a row of atoms being stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms.

5. The circuit of claim 4 , wherein the transpose read logic includes logic to select atoms in the slots, and store the selected atoms in a reshape circuit, and logic to transpose the selected atoms to form the output vectors of the transpose read of the matrix.

6. The circuit of claim 5 , wherein the reshape circuit includes a FIFO buffer having a depth at least as high as a maximum of M according to the data width of the elements of the matrix, and the logic to transpose the atoms includes a multiplexer tree configurable according to the data width.

7. The circuit of claim 5 , including logic to operate the reshape circuit using double buffering.

8. The circuit of claim 5 , wherein the transpose read logic is configurable for a selected one of a plurality of data types, and in which the data width differs for different data types in the plurality of data types.

9. The circuit of claim 3 , wherein the transpose read logic is configurable for a selected one of a plurality of data types, and the data widths differ for different data types in the plurality of data types, and the slot width is at least two times a maximum of the data width of data types in the plurality of data types.

10. A reconfigurable data processor, comprising:
an array of configurable units; and
a bus system connected to the array of configurable units which communicates data at a bus clock rate; wherein a configurable unit in the array of configurable units includes:
a memory array,
logic to write a matrix to the memory array at the bus clock rate, the matrix having elements with a data width having a number D of bits of data; and
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix at the bus clock rate,
wherein the transpose read logic and the normal read logic are operable on the memory array to output in parallel respective vectors in transposed and normal orders.

11. The reconfigurable data processor of claim 10 , including normal read logic configurable according to the data width, to output vectors of a normal read of the matrix at the bus clock rate, and wherein the memory array includes a first read port and a second read port, and the normal read port is operably coupled to the first read port, and the transpose read logic is operably coupled to the second read port.

12. A reconfigurable data processor, comprising:
an array of configurable units; and
a bus system connected to the array of configurable units which communicates data at a bus clock rate; wherein a configurable unit in the array of configurable units includes:
a memory array,
logic to write a matrix to the memory array at the bus clock rate, the matrix having elements with a data width having a number D of bits of data; and
transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix at the bus clock rate;
wherein the memory array includes a plurality of slots, where slots in the plurality of slots include having a slot width (number of columns) equal to a multiple M greater than 1 of the data width.

13. The reconfigurable data processor of claim 12 , wherein the transpose read logic includes write logic to organize sets of M rows of the matrix in the memory into a plurality of rows of atoms of M by M elements, atoms in a row of atoms being stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms.

14. The reconfigurable data processor of claim 13 , wherein the transpose read logic includes logic to select atoms in the slots, and store the selected atoms in a reshape circuit, the reshape circuit including circuits to transpose the selected atoms to form the output vectors of the transpose read of the matrix.

15. The reconfigurable data processor of claim 14 , wherein the reshape circuit includes a FIFO buffer having a depth at least as high as a maximum of M according to the data type of the elements of the matrix, and the circuit to transpose the atoms comprises a multiplexer tree configurable according to the data width.

16. The reconfigurable data processor of claim 14 , including logic to operate the reshape circuit using double buffering.

17. The reconfigurable data processor of claim 14 , wherein the transpose read logic is configurable for a selected one of a plurality of data types, and in which the data width differs for different data types in the plurality of data types.

18. The reconfigurable data processor of claim 12 , wherein the transpose read logic is configurable for a selected one of a plurality of data types, and in which the data width differs for different data types in the plurality of data types, and the slot width is at least two times a maximum of the data width of data types in the plurality of data types.

19. A memory circuit, comprising:
a memory array;
write logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data, wherein the memory array includes a plurality of slots readable in parallel on different rows, where slots in the plurality of slots have a slot width equal to a multiple M of the data width, with logic to organize, when M is greater than 1, sets of M rows of the matrix in the memory array into a plurality of rows of atoms of M by M elements, so that atoms in a row of atoms are stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms; and
transpose read logic to output vectors of a transpose read

Assignees

• Sambanova Systems Inc

Inventors

• Koeplinger David Alan
• Prabhakar Raghu
• Sivaramakrishnan Ram
• Jackson David Brian
• Luttrell Mark

Classifications

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G06F5/08

  having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register {(G06F5/065 takes precedence; shift registers per se G11C19/00)} · CPC title

• G06F7/78 Primary

  for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title