Semiconductor device including dummy metal

Patent metadata

Field	Value
Publication number	US-2017005100-A1
Application number	US-201615139444-A
Country	US
Kind code	A1
Filing date	Apr 27, 2016
Priority date	Jul 2, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

First claim

1 . A semiconductor device comprising:
a plurality of dummy wirings formed at different vertical levels on a substrate and electrically floated, each of the plurality of dummy wirings extending in a horizontal direction parallel to a top surface of the substrate; and a plurality of dummy contact plugs each connected between the plurality of dummy wirings, at least one of the plurality of dummy contact plugs connecting between two dummy wirings of the plurality of dummy wirings, and each of the plurality of dummy contact plugs having a rod shape extending in a vertical direction perpendicular to the top surface of the substrate, wherein no dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

2 . The semiconductor device of claim 1 , wherein at least two pairs of adjacent dummy wirings among the plurality of dummy wirings are respectively electrically connected via at least one of the plurality of dummy contact plugs.

3 . The semiconductor device of claim 1 , wherein at least first adjacent dummy wirings among the plurality of dummy wirings are electrically connected via at least two of the plurality of dummy contact plugs.

4 . The semiconductor device of claim 1 , wherein the dummy contact plugs include:
a dummy direct contact directly connecting at least one of the plurality of dummy wirings to the substrate.

5 . The semiconductor device of claim 4 , wherein at least two elements among the plurality of dummy wirings and the plurality of dummy contact plugs form a continuous material movement path to allow hydrogen to diffuse through the continuous material movement path.

6 . The semiconductor device of claim 4 , wherein the dummy direct contact is connected to a device isolation layer formed in the substrate or an active area defined by the device isolation layer in the substrate and is electrically floated in the substrate.

7 . The semiconductor device of claim 4 , wherein at least one of the plurality of dummy contact plugs other than the dummy direct contact does not overlap with the dummy direct contact in the vertical direction.

8 . The semiconductor device of claim 4 , wherein the substrate comprises a cell array region and a peripheral circuit region, and
wherein the plurality of dummy contact plugs are formed in the peripheral circuit region.

9 . The semiconductor device of claim 4 , wherein at least two elements among the plurality of dummy wirings and the plurality of dummy contact plugs form a continuous material movement path,
wherein the continuous material movement path includes at least n vertical sections perpendicular to the top surface of the substrate and at least m horizontal sections parallel to the top surface of the substrate, and wherein a total combined distance of the m sections is greater than or equal to a total combined distance of the n sections.

10 . The semiconductor device of claim 1 , wherein the plurality of dummy wirings comprise a plurality of first dummy wirings being spaced apart from each other on the substrate at a first vertical level and a second dummy wiring at a second vertical level different from the first vertical level, and
wherein the second dummy wiring is connected to the plurality of first dummy wirings via the plurality of dummy contact plugs.

11 . The semiconductor device of claim 1 , wherein at least two of the plurality of dummy wirings extend in different directions in relation to each other.

12 . The semiconductor device of claim 1 , wherein each of the dummy contact plugs has a rod shape extending in the vertical direction, and
wherein, in a plan view, a first width of each of the dummy contact plugs in a first direction and a second width of the each of the dummy contact plugs in a second direction perpendicular to the first direction are less than or equal to a width of each of the dummy wirings in the first direction.

13 . A semiconductor device comprising:
first, second, third, and fourth dummy wirings sequentially formed on a substrate from a low level, each of the first, second, third, and fourth dummy wirings extending in a horizontal direction parallel to a top surface of the substrate, and electrically floated; and a plurality of dummy contact plugs each electrically connecting adjacent dummy wirings among the first, second, third, and fourth dummy wirings, each of the plurality of dummy contact plugs extending in a vertical direction perpendicular to the top surface of the substrate, wherein no dummy wiring of the first, second, third, and fourth dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

14 . The semiconductor device of claim 13 , wherein the plurality of dummy contact plugs comprise a first dummy contact plug connecting the first and second dummy wirings and a second dummy contact plug connecting the third and fourth dummy wirings, and
wherein the second and third dummy wirings are not connected via at least one of the plurality of dummy contact plugs.

15 . The semiconductor device of claim 13 , wherein the substrate and the first dummy wiring are not electrically connected.

16 . A semiconductor device comprising:
a semiconductor substrate; a plurality of dummy metal lines formed at different vertical levels from the semiconductor substrate, each of the plurality of dummy metal lines extending in a horizontal direction parallel to a top surface of the semiconductor substrate; a plurality of insulating layers each disposed below a corresponding dummy metal line; and one or more dummy contact plugs extending in a vertical direction perpendicular to the top surface of the semiconductor substrate and electrically connecting at least two of the plurality of dummy metal lines, wherein at least one of the dummy metal lines extends in a different direction from others.

17 . The semiconductor device of claim 16 , further comprising:
a plurality of transistors formed on the semiconductor substrate, wherein no dummy metal line of the plurality of dummy metal lines is electrically connected to a terminal of any one of the plurality of transistors.

18 . The semiconductor device of claim 16 , wherein the plurality of dummy metal lines are not electrically connected to a voltage source or a ground.

19 . The semiconductor device of claim 16 , wherein two adjacent dummy metal lines of the plurality of dummy metal lines extend in a different direction in relation to each other.

20 . The semiconductor device of claim 16 , wherein at least two adjacent dummy metal lines are not electrically connected to each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Min Hee
• Yamada Satoru
• Lee Sung-Sam
• Lee Jung-Bun

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L27/10814

  Electricity · mapped topic

• H01L27/10897 Primary

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic