Power grid and standard cell co-design structure and methods thereof

Patent metadata

Field	Value
Publication number	US-10748889-B2
Application number	US-201916274229-A
Country	US
Kind code	B2
Filing date	Feb 12, 2019
Priority date	Jun 15, 2018
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

First claim

What is claimed is:

1. An apparatus comprising:
a metal layer having a metal pitch between metal elements;
a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is an unequal ratio of the metal pitch;
at least two power rails coupled, by via staples, with the metal layer, wherein a first set of via staples associated with a first power rail are unaligned with respect to a second set of via staples associated with a second power rail;
plurality of first standard cells, each respectively located in an even placement site wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples; and
plurality of second standard cells, one or more of the second standard cells being a shifted version of corresponding ones of the first standard cells, and each of the second standard cells is respectively located in an odd placement site wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

2. The apparatus of claim 1 , wherein each of the first plurality of standard cells include locations for via staples; and
wherein each of the second plurality of standard cells include locations for via staples that are shifted a number of gate electrode pitches from corresponding locations for via staples in the respective first plurality of standard cells.

3. The apparatus of claim 1 , wherein the via staples are located at regular intervals of a multiple of the metal pitch.

4. The apparatus of claim 1 , wherein the ratio of gate electrode pitch to metal pitch is such that three metal elements occur for every two gate electrode elements; and
wherein the via staples occur at a pitch which is a multiple of every third metal element.

5. The apparatus of claim 1 , wherein the via staple locations at least partially overlap the gate electrode locations.

6. The apparatus of claim 1 , wherein each of the standard cells include a spacing for the via staples; and
wherein a location of the spacing for the via staples determines whether the standard cell is included in the first plurality of standard cells or the second plurality of standard cells.

7. The apparatus of claim 6 , wherein each of the second plurality of standard cell includes a version of a corresponding one of the first plurality of standard cells that is shifted such that the location of the spacing for the via staple aligns with both a via staple and the gate electrode pitch.

8. The apparatus of claim 6 , further including a flipped plurality of standard cells that include mirrored versions of portions of the first plurality and the second plurality of standard cells, wherein each of the flipped plurality of standard cells includes a flipped version of a corresponding one of the standard cells that is flipped in such a way that the location of the spacing for the via staple aligns with both a via staple and the gate electrode pitch.

9. An apparatus comprising:
a processor that includes an integrated circuit formed, in part, of standard circuit cells powered by a power gird,
the integrated circuit comprising:
a metal layer having a metal pitch between metal elements;
a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is an unequal ratio of the metal pitch;
a power grid coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements;
at least two power rails coupled, by the via staples, with the metal layer, wherein a first set of via staples associated with a first power rail are unaligned with respect to a second set of via staples associated with a second power rail;
a first plurality of standard circuit cells, each respectively located such that portions of the standard cells that carry signals within the metal layer do not connect to the via staples; and

a second plurality of standard circuit cells, each of the second plurality of standard circuit cells is a shifted version of a corresponding one of the first plurality of standard circuit cells, and each of the second plurality of standard circuit cells is respectively located such that portions of the standard circuit cells that carry signals within the metal layer do not connect to the via staples.

10. The apparatus of claim 9 , wherein each of the first plurality of standard cells include locations for via staples, first gate electrode elements, and first metal elements; and
wherein each of the second plurality of standard cells include:
locations for via staples that are shifted a number of gate electrode pitches from corresponding locations for via staples in the respective first plurality of standard cells, and
second metal elements are placed differently than corresponding first metal elements in the respective first plurality of standard cells.

11. The apparatus of claim 9 , wherein the via staples are located at regular intervals of a multiple of the metal pitch.

12. The apparatus of claim 9 , wherein the ratio of gate electrode pitch to metal pitch is such that three metal elements occur for every two gate electrode elements; and
wherein the via staples occur at a pitch which is a multiple of every third metal element.

13. The apparatus of claim 9 , wherein each of the second plurality of standard circuit cells is a version shifted one gate electrode pitch from a corresponding one of the first plurality of standard circuit cells.

14. The apparatus of claim 9 , wherein each of the standard circuit cells include a spacing for the via staples; and
wherein a location of the spacing for the via staples determines whether the standard cell is included in the first plurality of standard circuit cells or the second plurality of standard circuit cells.

15. The apparatus of claim 14 , wherein each of the second plurality of standard cell includes a version of a corresponding one of the first plurality of standard circuit cells that is shifted such that the location of the spacing for the via staple aligns with both a via staple and the gate electrode pitch.

16. The apparatus of claim 14 , further including a third plurality of standard circuit cells that include mirrored versions of portions of the first plurality and the second plurality of standard circuit cells, wherein each of the third plurality of standard circuit cells includes a flipped version of a corresponding one of the standard circuit cells that is flipped in such a way that the location of the spacing for the via staple aligns with both a via staple and the gate electrode pitch.

17. An apparatus comprising:
a place-and-route tool configured to place standard circuit cells within a circuit design, the place-and-route tool configured to:
establish a metal layer having a metal pitch between metal elements;
establish a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is an unequal ratio of the metal pitch;
route at least one power rail coupled, by via staples, with the metal layer, wherein a first set of via staples associated with a first power rail are unaligned with respect to a second set of via staples associated with a second power rail;
place a first plurality of standard cells, each respectively located in a even first placement site wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples; and
place a second plurality of standard cells, one or more of the second plurality of standard

Assignees

• Samsung Electronics Co Ltd

Inventors

• Berzins Matthew
• Hoover Andrew Paul
• Peura Christopher Alan

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/90

  Masterslice integrated circuits · CPC title

• H10D89/00 Primary

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title

• H10D84/981

  Power supply lines · CPC title

• H10D84/975

  Wiring regions or routing · CPC title