Semiconductor chip including region having rectangular-shaped gate structures and first metal structures

Patent metadata

Field	Value
Publication number	US-9905576-B2
Application number	US-201715696728-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Mar 9, 2006
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by an as-fabricated gate pitch of less than or equal to about 193 nanometers, each gate structure layout shape in the region having a substantially rectangular shape and having an as-fabricated gate structure width of less than or equal to about 45 nanometers and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate structure layout shape positioned thereon, wherein each pair of gate structure layout shapes that are positioned in an end-to-end manner are separated from each other by an as-fabricated line end-to-line end gap of less than or equal to about 193 nanometers;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each first-metal structure layout shape in the region having at least one adjacent first-metal structure layout shape positioned next to each of its sides at an as-fabricated y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of first-metal structure layout shapes that are positioned in an end-to-end manner are separated by an as-fabricated line end-to-line end gap of less than or equal to about 193 nanometers;
at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein a portion of the logic circuit includes electrical connections that collectively include first-metal structures positioned on at least five of the at least eight first-metal gridlines.

2. The semiconductor chip as recited in claim 1 , wherein the region includes a second-metal layer including second-metal structures formed in part based on corresponding second-metal structure layout shapes used as an input to a lithography process, the second-metal structure layout shapes positioned in accordance with a second-metal horizontal grid, the second-metal horizontal grid including at least eight second-metal gridlines, each second-metal structure layout shape in the region having at least one adjacent second-metal structure layout shape positioned next to each of its sides at an as-fabricated x-coordinate spacing of less than or equal to 193 nanometers, each second-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated second-metal gridline, wherein at least eight of the at least eight second-metal gridlines have at least one second-metal structure layout shape positioned thereon, wherein each pair of second-metal structure layout shapes that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the second-metal layer is positioned second in the stack of metal layers counting upward from the top surfaces of the gate structures.

3. The semiconductor chip as recited in claim 2 , wherein each first-metal structure layout shape in the region has a width measured in the y-direction that is either a first width or a second width different than the first width.

4. The semiconductor chip as recited in claim 3 , wherein at least one gate structure within the region that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type is electrically connected to at least one gate structure within the region that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type through an electrical connection that includes at least one first-metal structure and at least one second-metal structure.

5. The semiconductor chip as recited in claim 2 , wherein the at least six contact structure layout shapes are positioned in accordance with a contact vertical grid, the contact vertical grid including contact gridlines extending in the x-direction, each of the at least six contact structure layout shapes positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated contact gridline, and at least two of the at least six contact structure layout shapes positioned to also extend lengthwise in the x-direction in a substantially centered manner along an associated first-metal gridline.

6. The semiconductor chip as recited in claim 2 , wherein each second-metal structure layout shape in the region is positioned next to at least one other second-metal structure layout shape on a first side in accordance with a second-metal pitch and is positioned next to at least one other second-metal structure layout shape on a second side in accordance with the second-metal pitch, wherein the second-metal pitch is measured in

Assignees

• Tela Innovations Inc

Inventors

• Becker Scott T
• Smayling Michael C

Classifications

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L2027/11875

  Electricity · mapped topic