Methods, apparatus and system for a passthrough-based architecture

Patent metadata

Field	Value
Publication number	US-2018033701-A1
Application number	US-201715728445-A
Country	US
Kind code	A1
Filing date	Oct 9, 2017
Priority date	Mar 11, 2016
Publication date	Feb 1, 2018
Grant date	—

Abstract

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

First claim

1 .- 10 . (canceled)

11 . A finFET device, comprising:
a first gate structure and a second gate structure on a semiconductor substrate; a first active area on one end of said first and second gate structures; a second active area on the other end of said first and second gate structures; and a self-aligned TS structure configured to operatively couple said first active area to said second active area.

12 . The finFET device of claim 11 , wherein said self-aligned TS structure is a borderless pass-through structure that provides a pass-through route between said first and second active areas.

13 . The finFET device of claim 11 , further comprising a CB structure above at least one of said gate structures, wherein said first CB structure is formed offset relative to said gate structure in a manner such that said first CB structure does not contact the TS structure.

14 . The finFET device of claim 13 , wherein CB structure is a self-aligned via defined in one direction by the borders of an M0 metal formation.

15 . The finFET device of claim 11 , wherein said first active area, said second active area and said TS structure each are defined by at least one of a plurality of cut masks.

16 . The finFET device of claim 11 , further comprising a CA structure, wherein said CA structure is formed to make contact with said TS structure and said first active area.

17 . The finFET device of claim 11 , wherein said first active area is a PMOS region and wherein said second active area is an NMOS region.

18 . A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device comprising at least one fin field effect transistor (finFET); and a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system; wherein said semiconductor device processing system is adapted to:
form a first gate structure and a second gate structure on a semiconductor wafer;
form a first active area on one end of said first and second gate structures;
form a second active area on the other end of said first and second gate structures; and
form a trench silicide (TS) structure self-aligned to said first and second gate structures, wherein said TS structure being configured to operatively couple said first active area to said second active area.

19 . The system of claim 18 , further comprising a design unit configured to generate a first design comprising a definition for a functional cell comprising said self-aligned TS structure, wherein data from said design unit is used by said process controller to control an operation of said semiconductor device processing system, and wherein said functional cell is a bit cell for a memory device.

20 . The system of claim 18 , wherein said semiconductor device processing system is further adapted to process semiconductor wafers to form functional cells characterized by a 10 nm architecture having 31.5 nm fin pitch in a 7.5 nm track design at 42 nm metal pitch for processing cross couple.

Assignees

• Globalfoundries Inc

Inventors

• Bouche Guillaume
• Neogi Tuhin Guha
• Wei Andy Chi-Hung
• Zeng Jia
• Kye Jongwook
• Stephens Jason Eugene
• Lin Irene Yuh-Ling
• Raghunathan Sudharshanan
• Yuan Lei

Classifications

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10W20/0698

  Local interconnections · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H10D84/853

  comprising FinFETs · CPC title