Semiconductor chip including integrated circuit defined within dynamic array section

Patent metadata

Field	Value
Publication number	US-9595515-B2
Application number	US-201414276528-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	Mar 7, 2007
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a region including at least nine linear-shaped conductive structures oriented to extend lengthwise in a first direction, the at least nine linear-shaped conductive structures positioned such that a distance as measured in a second direction perpendicular to the first direction between any two lengthwise-oriented centerlines of the at least nine linear-shaped conductive structures is substantially equal to an integer multiple of a gate electrode pitch,
the at least nine linear-shaped conductive structures including a first linear-shaped conductive structure that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
the at least nine linear-shaped conductive structures including a second linear-shaped conductive structure that forms a gate electrode of a second transistor of the first transistor type and a gate electrode of a second transistor of the second transistor type,
the at least nine linear-shaped conductive structures including a third linear-shaped conductive structure that forms a gate electrode of a third transistor of the first transistor type and a gate electrode of a third transistor of the second transistor type,
the at least nine linear-shaped conductive structures including a fourth linear-shaped conductive structure that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
the first and second linear-shaped conductive structures positioned such that their lengthwise-oriented centerlines are separated by a distance as measured in the second direction substantially equal to the gate electrode pitch,
the third and fourth linear-shaped conductive structures positioned such that their lengthwise-oriented centerlines are separated by a distance as measured in the second direction substantially equal to the gate electrode pitch,
the first and third linear-shaped conductive structures positioned such that their lengthwise-oriented centerlines are substantially co-aligned in the first direction, the first and third linear-shaped conductive structures separated from each other by a first end-to-end spacing as measured in the second direction,
the second and fourth linear-shaped conductive structures positioned such that their lengthwise-oriented centerlines are substantially co-aligned in the first direction, the second and fourth linear-shaped conductive structures separated from each other by a second end-to-end spacing as measured in the second direction,
the first end-to-end spacing substantially equal to the second end-to-end spacing.

2. A semiconductor chip as recited in claim 1 , wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by a first portion of the region that does not include a source or a drain of any transistor.

3. A semiconductor chip as recited in claim 2 , wherein the third and fourth transistors of the first transistor type are collectively separated from the third and fourth transistors of the second transistor type by a second portion of the region that does not include a source or a drain of any transistor.

4. A semiconductor chip as recited in claim 3 , wherein the first and second transistors of the second transistor type are collectively separated from the third and fourth transistors of the first transistor type by a third portion of the region that does not include a source or a drain of any transistor.

5. A semiconductor chip as recited in claim 1 , further comprising:
a first contact structure in physical contact with the first linear-shaped conductive structure at a location on the first linear-shaped conductive structure between the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type.

6. A semiconductor chip as recited in claim 5 , further comprising:
a second contact structure in physical contact with the second linear-shaped conductive structure at a location on the second linear-shaped conductive structure between the gate electrode of the second transistor of the first transistor type and the gate electrode of the second transistor of the second transistor type.

7. A semiconductor chip as recited in claim 6 , wherein the first contact structure has a second direction-oriented centerline extending in the second direction, wherein the second contact structure has a second direction-oriented centerline extending in the second direction, wherein the second direction-oriented centerline of the first contact structure is offset in the first direction from the second direction-oriented centerline of the second contact structure.

8. A semiconductor chip as recited in claim 6 , wherein the first contact structure has a second direction-oriented centerline extending in the second direction, wherein the second contact structure has a second direction-oriented centerline extending in the second direction, wherein a second direction-oriented centerline of the first contact structure is substantially co-aligned with a second direction-oriented centerline of the second contact structure.

9. A semiconductor chip as recited in claim 6 , further comprising:
a third contact structure in physical contact with the third linear-shaped conductive structure at a location on the third linear-shaped conductive structure between the gate electrode of the third transistor of the first transistor type and the gate electrode of the third transistor of the second transistor type; and
a fourth contact structure in physical contact with the fourth linear-shaped conductive structure at a location on the fourth linear-shaped conductive structure between the gate electrode of the fourth transistor of the first transistor type and the gate electrode of the fourth transistor of the second transistor type.

10. A semiconductor chip as recited in claim 1 , wherein a size of the first transistor of the first transistor type as measured in the first direction is different than a size of the second transistor of the first transistor type as measured in the first direction, and wherein a size of the first transistor of the second transistor type as measured in the first direction is different than a size of the second transistor of the second transistor type as measured in the first direction.

11. A semiconductor device, comprising:
a first transistor of a first transistor type;
a second transistor of the first transistor type;
a first transistor of a second transistor type;
a second transistor of the second transistor type,
wherein the first and second transistors of the first transistor type share a diffusion region of a first diffusion type,
wherein the first and second transistors of the second transistor type share a diffusion region of a second diffusion type,
wherein the first transistor of the first transistor type includes a gate electrode formed from a first conductive structure, and wherein the first transistor of the second transistor type includes a gate electrode formed from the first conductive structure, wherein the first conductive structure has a linear-shape when viewed from above such that the first conductive structure is devoid of a substantial change in direction along its length, and
wherein the second transistor of the first transistor type includes a gate electrode formed from a second conductive structure, and wherein the second transistor of the second transistor type also includes a gate electrode formed from the

Assignees

• Tela Innovations Inc

Inventors

• Becker Scott T
• Smayling Michael C

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• Y02P90/265

  Cross-Sectional Technologies · mapped topic