Vertical transport logic circuit cell with shared pitch

Patent metadata

Field	Value
Publication number	US-10742218-B2
Application number	US-201816042927-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Jul 23, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a vertical transport logic circuit cell comprising a first logic gate and at least a second logic gate positioned in an overlapping configuration, the first logic gate comprising at least one input terminal and at least one output terminal; the second logic gate comprising at least one input terminal and at least one output terminal;
wherein one of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate.

2. The semiconductor structure of claim 1 , wherein the pitch is a contacted polysilicon pitch.

3. The semiconductor structure of claim 1 , wherein, when the input terminal of the first logic gate and the input terminal of the second logic gate share a pitch of the vertical transport logic circuit cell, the first logic gate uses an upper vertical portion of the shared pitch and the second logic gate uses a lower vertical portion of the shared pitch.

4. The semiconductor structure of claim 1 , wherein, when the input terminal of the first logic gate and the input terminal of the second logic gate share a pitch of the vertical transport logic circuit cell, the first logic gate uses a lower vertical portion of the shared pitch and the second logic gate uses an upper vertical portion of the shared pitch.

5. The semiconductor structure of claim 1 , wherein, when the output terminal of the first logic gate and the output terminal of the second logic gate share the pitch of the vertical transport logic circuit cell, the first logic gate uses a conductive layer below an interconnect layer for an output terminal with a cell strap and the second logic gate uses a conductive layer above the interconnect layer with a cell strap for an output terminal.

6. The semiconductor structure of claim 1 , wherein, when the first logic gate comprises at least one p-type field effect transistor and at least one n-type field effect transistor, the p-type field effect transistor is connected to the n-type field effect transistor using a cell strap.

7. The semiconductor structure of claim 6 , wherein, when the second logic gate comprises at least one p-type field effect transistor and at least one n-type field effect transistor, the p-type field effect transistor is connected to the n-type field effect transistor using a given metallization layer.

8. The semiconductor structure of claim 1 , wherein the vertical transport logic circuit cell comprises two or more of the same type of logic gate.

9. The semiconductor structure of claim 1 , wherein the vertical transport logic circuit cell comprises two or more different types of logic gates.

10. The semiconductor structure of claim 1 , wherein the vertical transport logic circuit cell comprises a NAND2 logic circuit such that the first logic gate is a first NAND gate and the second logic gate is a second NAND gate.

11. An integrated circuit, comprising:
one or more vertical transport logic circuit cells, wherein at least one of the one or more vertical transport logic circuit cells comprises a first logic gate and at least a second logic gate positioned in an overlapping configuration, the first logic gate comprising at least one input terminal and at least one output terminal; the second logic gate comprising at least one input terminal and at least one output terminal;
wherein one of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate.

12. The integrated circuit of claim 11 , wherein the pitch is a contacted polysilicon pitch.

13. The integrated circuit of claim 11 , wherein, when the input terminal of the first logic gate and the input terminal of the second logic gate share a pitch of the vertical transport logic circuit cell, the first logic gate uses an upper vertical portion of the shared pitch and the second logic gate uses a lower vertical portion of the shared pitch.

14. The integrated circuit of claim 11 , wherein, when the input terminal of the first logic gate and the input terminal of the second logic gate share a pitch of the vertical transport logic circuit cell, the first logic gate uses a lower vertical portion of the shared pitch and the second logic gate uses an upper vertical portion of the shared pitch.

15. The integrated circuit of claim 11 , wherein, when the output terminal of the first logic gate and the output terminal of the second logic gate share the pitch of the vertical transport logic circuit cell, the first logic gate uses a conductive layer below an interconnect layer for an output terminal with a cell strap and the second logic gate uses another conductive layer above the interconnect layer with a cell strap for an output terminal.

16. The integrated circuit of claim 11 , wherein, when the first logic gate comprises at least one p-type field effect transistor and at least one n-type field effect transistor, the p-type field effect transistor is connected to the n-type field effect transistor using a cell strap.

17. The integrated circuit of claim 16 , wherein, when the second logic gate comprises at least one p-type field effect transistor and at least one n-type field effect transistor, the p-type field effect transistor is connected to the n-type field effect transistor using a given metallization layer.

18. The integrated circuit of claim 11 , wherein the vertical transport logic circuit cell comprises two or more of the same type of logic gate.

19. The integrated circuit of claim 11 , wherein the vertical transport logic circuit cell comprises two or more different types of logic gates.

20. The integrated circuit of claim 11 , wherein the vertical transport logic circuit cell comprises a NAND2 logic circuit such that the first logic gate is a first NAND gate and the second logic gate is a second NAND gate.

21. A method for fabricating a semiconductor structure, comprising:
in a vertical transport logic circuit cell comprising a first logic gate and at least a second logic gate positioned in an overlapping configuration, wherein the first logic gate comprises at least one input terminal and at least one output terminal, and the second logic gate comprises at least one input terminal and at least one output terminal;
sharing a pitch of the vertical transport logic circuit cell between one of the input terminal and the output terminal of the first logic gate and one of the input terminal and the output terminal of the second logic gate.

22. The method of claim 21 , wherein the pitch is a contacted polysilicon pitch.

23. The method of claim 21 , wherein at least one of the first logic gate and the second logic gate comprise: an inverter logic gate; a NAND logic gate; an AND logic gate; a NOR logic gate; an OR logic gate; an AND-OR logic gate; an OR-AND logic gate; a buffer; a flip-flop; and a multiplexer.

24. A semiconductor structure, comprising:
a vertical transport logic circuit cell comprising a first logic gate and at least a second logic gate positioned in an overlapping configuration;
wherein the first logic gate and the second logic gate share a pitch of the vertical transport logic circuit cell.

25. The semiconductor structure of claim 24 , wherein the pitch is a contacted polysilicon pitch.

Assignees

• IBM
• Int Business Machines Corpoartion

Inventors

• Anderson Brent A
• Chu Albert

Classifications

• H10D84/951

  Technology used, i.e. design rules · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/962

  Horizontal or vertical grid line density · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title