High density vertical field effect transistor multiplexer

Patent metadata

Field	Value
Publication number	US-9859898-B1
Application number	US-201615282027-A
Country	US
Kind code	B1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method for forming a multiplexor integrated circuit includes employing four complementary pairs of vertical field effect transistor (VFET) pairs, each of the complementary pairs of VFETs includes a first VFET device having a gate and a second VFET device having a gate, the gate of the first VFET device is connected to the gate of the second VFET device. The four complementary pairs VFET pairs are arranged to form a signal input portion of the multiplexor with four contact poly pitch (CPP) The plurality source/drain connections are operably connected.

First claim

What is claimed is:

1. A method of forming a multiplexor integrated circuit, the method comprising:
employing four complementary pairs of vertical field effect transistor (VFET) devices, each complementary pair of VFET devices of the four complementary pairs of VFET devices including a first VFET device having a gate and first source/drain regions and a second VFET device having a gate and second source/drain regions, wherein the gate of the first VFET device is connected to the gate of the second VFET device;
arranging the four complementary pairs to form a signal input portion of the multiplexor with four contact-to-poly pitch (CPP);
interconnecting a plurality of the first source/drain regions to each other;
interconnecting a plurality of the second source/drain regions to each other; and
interconnecting at least one of the first source/drain regions to at least one of the second source/drain regions.

2. The method according to claim 1 , further comprising employing another pair of complementary vertical field effect transistor (VFET) devices, wherein the another pair of complementary of vertical field effect transistor (VFET) devices is arranged as a select input inverter.

3. The method according to claim 2 , further comprising employing another pair of complementary vertical field effect transistor (VFET) devices, wherein the another pair of complementary vertical field effect transistor (VFET) devices is arranged as an output inverter.

4. The method according to claim 3 wherein the arranging results in a 2:1 multiplexor.

5. The method according to claim 1 wherein the arranging does not include a gate cross-couple.

6. The method according to claim 1 wherein the arranging results in at least two complementary pairs of vertical field effect transistor (VFET) devices sharing adjacent source/drain region interconnections to a power and a ground connection.

7. The method according to claim 1 , further comprising employing another pair of complementary vertical field effect transistor (VFET) devices, wherein the another pair of complementary vertical field effect transistor (VFET) devices is connected in parallel to a pair of vertical field effect (VFET) devices arranged as an output inverter to increase output drive capability of the multiplexor.

8. A multiplexor integrated circuit comprising:
four complementary pairs of vertical field effect transistor (VFET) devices, each complementary pair of VFET devices of the four complementary pairs of VFET devices including a first VFET device having a gate and first source/drain regions and a second VFET device having a gate and second source/drain regions, wherein the gate of the first VFET device is connected to the gate of the second VFET device, a plurality of the first source/drain regions are interconnected to each other, a plurality of the second source/drain regions are interconnected to each other, and at least one of the first source/drain regions is interconnected to at least one of the second source/drain regions;
wherein the four pairs of complementary VFET devices are arranged with interconnections to form a signal input portion of the multiplexor with four contact-to-poly pitch (CPP).

9. The multiplexor integrated circuit according to claim 8 , further comprising another pair of complementary vertical field effect transistor (VFET) devices, wherein the another pair of complementary vertical field effect transistor (VFET) devices is arranged as a select input inverter.

10. The multiplexor integrated circuit according to claim 9 , further comprising another pair of complementary vertical field effect transistor (VFET) devices, wherein the another pair of complementary vertical field effect transistor (VFET) devices is arranged as an output inverter.

11. The multiplexor integrated circuit according to claim 10 , wherein the multiplexor integrated circuit forms a 2:1 multiplexor.

12. The multiplexor integrated circuit according to claim 8 , wherein the multiplexor is formed without a gate cross-couple.

13. The multiplexor integrated circuit according to claim 8 , wherein two complementary pairs of vertical field effect transistor (VFET) devices share adjacent source/drain interconnections to a power and a ground connection.

Assignees

• IBM

Inventors

• Anderson Brent A
• Chu Albert M

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H03K19/17796 Primary

  for physical disposition of blocks · CPC title