High density programmable e-fuse co-integrated with vertical FETs

Patent metadata

Field	Value
Publication number	US-9728542-B1
Application number	US-201615164420-A
Country	US
Kind code	B1
Filing date	May 25, 2016
Priority date	May 25, 2016
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

First claim

What is claimed is:

1. A method for integrating vertical transistor and vertical electric fuses comprising:
forming fins through a dielectric layer and a dummy gate stack on a substrate, the dummy gate stack including a bottom spacer, a dummy gate layer and a top spacer layer;
thinning top portions of the fins by an etch process;
epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region;
removing the dummy gate layer and exposing sidewalls of the fins;
blocking the fuse region to form a gate structure in the transistor region;
blocking the transistor region and exposing the fuse region;
conformally depositing a metal on exposed sidewalls of the fins in the fuse region;
annealing the metal to form silicided fins to form fuses in the fuse region; and
separating portions of the substrate to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

2. The method as recited in claim 1 , wherein forming fins through the dummy gate stack on the substrate includes epitaxially growing the fins from the substrate through fin trenches formed through the dielectric layer and dummy stack.

3. The method as recited in claim 1 , wherein the dummy stack includes amorphous silicon and forming fins through the dummy gate stack includes oxidizing the amorphous silicon in the dummy gate layer to permit removal of the dummy gate layer.

4. The method as recited in claim 1 , wherein the gate structure includes a gate dielectric and a gate conductor vertically disposed on the fins in the transistor region.

5. The method as recited in claim 1 , further comprising forming a gate contact that lands on the gate conductor through an interlevel dielectric layer formed on the vertical transistors.

6. The method as recited in claim 1 , further comprising:
recessing the fins down into the dielectric layer;
filling recesses above the fins with a dielectric fill; and
removing the dielectric layer.

7. The method as recited in claim 6 , further comprising:
removing the dielectric fill to form contact holes; and
filling the contact holes to form contacts to the bottom source/drain regions and the bottom cathode/anode regions.

8. The method as recited in claim 1 , wherein separating portions of the substrate includes etching trenches between the transistor region and the fuse region and forming a shallow trench isolation region in the trenches.

9. The method as recited in claim 1 , further comprising:
encapsulating the source/drain regions and cathode/anode regions with a dielectric cap down to the top spacer layer; and
etching with the dielectric caps as an etch mask to expose the bottom spacer layer.

10. A method for integrating vertical transistor and vertical electric fuses comprising:
forming fins through a dielectric layer and a dummy gate stack on a substrate, the dummy gate stack including a bottom spacer, a dummy gate layer and a top spacer layer;
recessing the fins down into the dielectric layer;
filling recesses above the fins with a dielectric fill;
removing the dielectric layer;
thinning top portions of the fins by an etch process;
epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region;
encapsulating the source/drain regions and cathode/anode regions with a dielectric cap down to the top spacer layer;
etching with the dielectric caps as an etch mask to expose the bottom spacer layer;
removing the dummy gate layer and exposing sidewalls of the fins;
blocking the fuse region to form a gate structure in the transistor region;
blocking the transistor region and exposing the fuse region;
conformally depositing a metal on exposed sidewalls of the fins in the fuse region;
annealing the metal to form silicided fins to fork fuses in the fuse region; and
separating portions of the substrate to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

11. The method as recited in claim 10 , wherein forming fins through the dummy gate stack on the substrate includes epitaxially growing the fins from the substrate through fin trenches formed through the dielectric layer and dummy stack.

12. The method as recited in claim 10 , wherein the dummy stack includes amorphous silicon and forming fins through the dummy gate stack includes oxidizing the amorphous silicon in the dummy gate layer to permit removal of the dummy gate layer.

13. The method as recited in claim 10 , wherein the gate structure includes a gate dielectric and a gate conductor.

14. The method as recited in claim 10 , further comprising forming a gate contact that lands on the gate conductor through an interlevel dielectric layer formed on the vertical transistors.

15. The method as recited in claim 10 , further comprising: removing the dielectric fill to form contact holes; and filling the contact holes to form contacts to the bottom source/drain regions and the bottom cathode/anode regions.

16. The method as recited in claim 10 , wherein separating portions of the substrate includes etching trenches between the transistor region and the fuse region and forming a shallow trench isolation region in the trenches.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Guillorn Michael A
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L27/11206 Primary

  Electricity · mapped topic