Memory device and forming method thereof

Patent metadata

Field	Value
Publication number	US-10651193-B2
Application number	US-201816047308-A
Country	US
Kind code	B2
Filing date	Jul 27, 2018
Priority date	Jun 12, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate having a plurality of recess in a surface of the substrate;
an epitaxially-grown material formed in the plurality of recesses;
a first layer stack disposed on the substrate, the first layer stack comprising alternating conductor layers and dielectric layers;
a silicon carbide layer disposed on a top surface of the first layer stack;
a second layer stack disposed over the silicon carbide layer, the second layer stack comprising alternating conductor layers and dielectric layers;
one or more first structures extending orthogonally with respect to the surface of the substrate through the first layer stack and over the epitaxially-grown material disposed in the plurality of recesses; and
one or more second structures extending orthogonally with respect to the surface of the substrate through the second layer stack, the one or more second structures being substantially aligned over corresponding ones of the one or more first structures.

2. The memory device of claim 1 , wherein the one or more first structures comprises one or more NAND strings.

3. The memory device of claim 2 , wherein the one or more second structures comprises one or more NAND strings.

4. The memory device of claim 3 , wherein each of the one or more NAND strings comprises an inner semiconductor channel and one or more outer dielectric layers.

5. The memory device of claim 4 , wherein the one or more outer dielectric layers includes at least one oxide layer and at least one nitride layer.

6. The memory device of claim 1 , wherein the silicon carbide layer includes one or more doped regions substantially aligned over the one or more first structures.

7. The memory device of claim 6 , wherein the one or more doped regions are doped with carbon.

8. The memory device of claim 1 , wherein the silicon carbide layer has a thickness between 10 nm and 500 nm.

9. The memory device of claim 1 , wherein the first layer stack and the second layer stack each include alternating layers of oxide and tungsten.

10. The memory device of claim 1 , wherein the first layer stack and the second layer stack are arranged in a staircase pattern.

11. A method for forming a memory device, comprising:
forming a first layer stack over a substrate, the first layer stack having alternating sacrificial and dielectric layers;
forming one or more first openings through the first layer stack, the one or more first openings forming corresponding recesses in the substrate;
forming a material in the corresponding recesses;
forming one or more first vertical structures in the one or more first openings;
forming a silicon carbide layer on a top surface of the first layer stack;
forming a second layer stack over the silicon carbide layer, the second layer stack having alternating sacrificial and dielectric layers;
forming one or more second openings through the second layer stack, the one or more second openings being aligned with the one or more first vertical structures; and
forming one or more second vertical structures in the one or more second openings.

12. The method of claim 11 , wherein forming the material comprises forming epitaxially grown silicon in the corresponding recesses.

13. The method of claim 11 , further comprising:
removing the sacrificial layers from the first layer stack and the second layer stack, and replacing the removed sacrificial layers with conductive layers.

14. The method of claim 13 , wherein the removing the sacrificial layers comprises removing nitride layers from the first layer stack and the second layer stack, and wherein the replacing comprises replacing the nitride layers with tungsten.

15. The method of claim 11 , wherein forming the one or more first vertical structures comprises forming one or more NAND strings.

16. The method of claim 15 , wherein forming the one or more second vertical structures comprises forming one or more NAND strings.

17. The method of claim 16 , wherein forming the one or more NAND strings of the first and second vertical structures comprises forming one or more outer dielectric layers and forming a semiconductor channel.

18. The method of claim 17 , wherein forming one or more outer dielectric layers comprises forming at least one oxide layer and at least one nitride layer.

19. The method of claim 11 , wherein forming the silicon carbide layer comprises doping one or more regions of the silicon carbide layer, the one or more regions being substantially aligned over corresponding ones of the one or more first vertical structures.

20. The method of claim 19 , wherein the doping comprises doping the one or more regions of the silicon carbide layer with carbon.

21. The method of claim 11 , wherein forming the silicon carbide layer comprises forming the silicon carbide layer using plasma-enhanced chemical vapor deposition (PECVD).

22. The method of claim 11 , further comprising:
after forming the silicon carbide layer, annealing the memory device.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xiao li hong
• Wang Enbo
• Tang Zhao Hui
• Tao Qian
• Zhou yu ting
• Li Sizhe
• Li Zhaosong
• Liu Sha Sha

Classifications

• H01L21/76816

  Electricity · mapped topic

• H01L23/5329

  Electricity · mapped topic

• H01L21/02274

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L21/324

  Electricity · mapped topic