Three-dimensional semiconductor memory devices and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9356033-B2
Application number	US-201514810845-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Mar 3, 2010
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

First claim

What is claimed is:

1. A method for forming a three-dimensional semiconductor memory device, comprising:
forming dielectric layers and sacrificial layers that are alternately and repeatedly stacked over the substrate;
forming a groove penetrating the dielectric layers and the sacrificial layers;
forming first dielectric patterns and first sacrificial patterns that are alternately stacked at one side of the groove, and second dielectric patterns and second sacrificial patterns that are alternately stacked at the other side of the groove, by forming a trench penetrating the dielectric layers and the sacrificial layers having the groove;
replacing the first sacrificial patterns and second sacrificial patterns with first gates and second dates, respectively, the first gates comprising a plurality of first cell gates being stacked and a string selection gate over an uppermost first cell gate, and the second gates comprising a plurality of second cell gates being stacked and a ground selection gate over an uppermost second cell gate;
forming an active structure comprising a first vertical-type active portion and a second vertical-type active portion in the groove, the first vertical-type active portion overlapping sidewalls of the first gates, and the second vertical-type active portion overlapping sidewalls of the second gates; and
forming a conjunction doped region in the substrate, the conjunction doped region being connected to lower ends of the first and second vertical-type active portions.

2. The method of claim 1 , further comprising:
forming a bit line electrically connected to an upper end of the first vertical-type active portion; and
forming a source line electrically connected to an upper end of the second vertical-type active portion.

3. The method of claim 2 , wherein the bit line and the source line are located at different level with respect to a top surface of the substrate.

4. The method of claim 1 , wherein the forming of the active structure comprises:
forming a preliminary active structure comprising a first preliminary active portion contacting a first sidewall of the groove and a second preliminary active portion contacting a second sidewall of the groove, and
wherein the active structure is formed of portions of the preliminary active structure.

5. The method of claim 4 , wherein the forming of the conjunction doped region comprises:
forming a preliminary doped region in the substrate under the groove by implanting dopant ions through the groove before the preliminary active structure is formed; and
forming the conjunction doped region in the substrate under the active structure, by removing the preliminary doped region at both side of the active structure after the active structure is formed.

6. The method of claim 1 , wherein the conjunction doped region is formed in the substrate before the dielectric layers and the sacrificial layers are formed, and the groove exposes the conjunction doped region.

7. The method of claim 6 , further comprising forming a field dielectric pattern defining a base active portion in the substrate, wherein the conjunction doped region is formed in the base active portion.

8. A method for forming a three-dimensional semiconductor memory device, comprising:
forming dielectric layers and sacrificial layers that are alternately and repeatedly stacked over the substrate;
forming a first channel hole and a second channel hole that penetrate the dielectric layers and the sacrificial layers and are laterally spaced from each other;
forming a first vertical-type active portion and a second vertical-type active portion in the first channel hole and the second channel hole, respectively;
forming first dielectric patterns and first sacrificial patterns that are alternately stacked and have the first channel hole, and second dielectric patterns and second sacrificial patterns that are alternately stacked and have the second channel hole, by forming a trench penetrating the dielectric layers and the sacrificial layers having the first and second vertical-type active portions;
replacing the first sacrificial patterns and second sacrificial patterns with first gates and second gates, respectively, the first gates comprising a plurality of first cell gates being stacked and a string selection gate over an uppermost first cell gate, and the second gates comprising a plurality of second cell gates being stacked and a ground selection gate over an uppermost second cell gate; and
forming a conjunction doped region in the substrate, the conjunction doped region being connected to lower ends of the first and second vertical-type active portions.

9. The method of claim 8 , wherein the conjunction doped region is formed in the substrate before the dielectric layer and the sacrificial layers are formed, and the first and second channel holes expose portions of the conjunction doped region, respectively.

10. The method of claim 9 , further comprising forming a field dielectric pattern defining a base active portion in the substrate, wherein the conjunction doped region is formed in the base active portion.

11. The method of claim 1 , wherein replacing the first sacrificial patterns and second sacrificial patterns with the first gates and the second gates, respectively, comprises:
forming first empty regions and second empty regions by removing the first sacrificial patterns and the second sacrificial patterns; and
forming first gates respectively disposed in the first empty regions and second gates respectively disposed in the second empty regions.

12. The method of claim 11 , further comprising forming a gate dielectric layer in the first and second empty regions before the formation of the first gates respectively disposed in the first empty regions and the second gates respectively disposed in the second empty regions.

13. The method of claim 8 , further comprising:
forming a bit line electrically connected to an upper end of the first vertical-type active portion; and
forming a source line electrically connected to an upper end of the second vertical-type active portion.

14. The method of claim 13 , wherein the bit line and the source line are located at a different level with respect to a top surface of the substrate.

15. The method of claim 8 , wherein replacing the first sacrificial patterns and second sacrificial patterns with the first gates and the second gates, respectively, comprises:
forming first empty regions and second empty regions by removing the first sacrificial patterns and the second sacrificial patterns; and
forming first gates respectively disposed in the first empty regions and second gates respectively disposed in the second empty regions.

16. The method of claim 15 , further comprising forming a gate dielectric layer in the first and second empty regions before the formation of the first gates respectively disposed in the first empty regions and the second gates respectively disposed in the second empty regions.

Assignees

• Son Yong-Hoon
• Kim Jung Ho
• Baik Seungjae
• Lee Myoungbum
• Hwang Kihyun
• Samsung Electronics Co Ltd

Inventors

• Son Yong-Hoon
• Kim Jung Ho
• Baik Seungjae
• Lee Myoungbum
• Hwang Kihyun

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H01L27/11578

  Electricity · mapped topic

• H01L27/11551 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic