Three dimensional memory structure

Patent metadata

Field	Value
Publication number	US-9129859-B2
Application number	US-201313786925-A
Country	US
Kind code	B2
Filing date	Mar 6, 2013
Priority date	Mar 6, 2013
Publication date	Sep 8, 2015
Grant date	Sep 8, 2015

Abstract

A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

First claim

What is claimed is:

1. A method to fabricate a three dimensional memory structure comprising:
forming an array stack;
creating a layer of sacrificial material above the array stack;
etching a hole through the layer of sacrificial material and at least a portion of the array stack;
creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use said pillar as a common body;
removing at least some of the layer of sacrificial material around said pillar to expose at least a portion of said pillar;
etching away some of the exposed portion of said pillar; and
forming a field effect transistor (FET) using the exposed portion of said pillar as a body of the FET.

2. The method of claim 1 , wherein the sacrificial material comprises a silicon nitride.

3. The method of claim 1 , wherein the semiconductor material comprises polysilicon; and
wherein said forming of the FET comprises:
creating a gate oxide film on exposed surfaces of said pillar;
forming a polysilicon control gate around the exposed portion of said pillar;
forming an insulating layer above the polysilicon control gate; and
implanting a top portion of said pillar with an N+ dopant.

4. The method of claim 3 , further comprising:
recessing the polysilicon control gate before forming the insulating layer above the polysilicon control gate; and
planarizing to level the insulating layer with said pillar.

5. The method of claim 3 , further comprising recessing said pillar and forming a cap of oxide on top of said pillar before said removing of the at least some of the layer of sacrificial material.

6. The method of claim 5 , further comprising:
isotropically etching away a portion of the cap of insulating material to create an etch mask for said pillar; and
anisotropically etching away a portion of said pillar not protected by the cap of insulating material before the formation of the FET.

7. The method of claim 1 , wherein the semiconductor material comprises polysilicon; and
wherein said forming of the FET comprises:
creating a gate oxide film on exposed surfaces of said pillar;
forming a polysilicon control gate around the exposed portion of said pillar;
planarizing to level the polysilicon control gate with said pillar;
forming an insulating layer over the polysilicon control gate and said pillar;
etching an opening through the insulating layer, wherein the opening is no larger than a top surface of said pillar, and the opening is positioned over said pillar;
filling the opening with polysilicon; and
creating a heavily doped region in the polysilicon in the opening and a top portion of said pillar.

8. The method of claim 7 , wherein the insulating layer comprises silicon nitride; and
wherein said creating of said heavily doped region comprises:
implanting the semiconductor material in the opening with an N+ dopant; and
annealing the semiconductor material to diffuse the dopant to edges of said pillar.

9. The method of claim 1 , further comprising forming charge storage mechanisms in the hole before creating said pillar, wherein a charge storage mechanism comprises a conductive floating gate or a non-conductive charge trapping layer.

10. The method of claim 1 , further comprising:
depositing one or more films inside the hole; and
etching inside the hole for one or more periods.

Assignees

• Intel Corp

Inventors

• Liu Haitao
• Mouli Chandra V
• Parat Krishna K
• Sun Jie
• Huang Guangyu

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title