Self-aligned contact for trench power MOSFET

Patent metadata

Field	Value
Publication number	US-10644118-B2
Application number	US-201715623303-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Apr 8, 2015
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1. A device, comprising:
a semiconductor substrate;
a plurality of gate trenches formed in the semiconductor substrate, each gate trench being lined with an insulating material along sidewalls inside the gate trench, each gate trench having a conductive material in the gate trench; and
a plurality of contact structures, each contact structure being formed adjacent to a corresponding one of the plurality of gate trenches and each contact structure including a contact trench filled with one or more conductive materials;
a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between adjacent contact structures of the plurality of contact structures, and wherein the layer of nitride has a recess on a top surface of the nitride layer over the conductive material in the gate trenches, wherein the recess contains portions of the conductive material that fills the contact structures; and
a metal layer formed over the layer of nitride.

2. The device of claim 1 , wherein the insulating material along sidewalls inside each gate trench has a thicker portion along the sidewalls inside a lower portion of the gate trench and a thinner insulating material along the sidewalls inside an upper portion of the gate trench.

3. The device of claim 2 , wherein the thicker portion of the insulating material has a thickness that is about 2 to 5 times of a thickness of the thinner portion.

4. The device of claim 1 , wherein the conductive material in each gate trench has a bottom portion of the conductive material in a lower portion of the gate trench and a top portion of the conductive material in an upper portion of the gate trench, the bottom and the top portions of the conductive materials being separated by an inter-electro insulating layer.

5. The device of claim 4 , wherein the bottom and top portions of the conductive material are electrically connected.

6. A device, comprising:
a semiconductor substrate;
a plurality of gate trenches formed in the semiconductor substrate, each gate trench being lined with an insulating material along sidewalls inside the gate trench, each gate trench having a conductive material in the gate trench; and
a plurality of contact structures, each contact structure being formed adjacent to a corresponding one of the plurality of gate trenches and each contact structure including a contact trench filled with one or more conductive materials,
a non-uniform oxide layer provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures, wherein the non-uniform oxide layer is characterized by a greater elevation of oxide at corners of the mesas than at a central portion over the conductive material in the gate trenches; and
a metal layer formed over the non-uniform oxide layer.

7. The device of claim 6 , wherein the oxide layer is in a thickness of about of 0.050 μm to about 0.300 μm.

8. The device of claim 6 , wherein the insulating material along sidewalls inside each gate trench has a thicker portion along the sidewalls inside a lower portion of the gate trench and a thinner insulating material along the sidewalls inside an upper portion of the gate trench.

9. The device of claim 8 , wherein the thicker portion of the insulating material has a thickness that is about 2 to 5 times of a thickness of the thinner portion.

10. The device of claim 6 wherein the conductive material in each gate trench has a bottom portion of the conductive material in a lower portion of the gate trench and a top portion of the conductive material in an upper portion of the gate trench, the bottom and the top portions of the conductive materials being separated by an inter-electro insulating layer.

11. The device of claim 10 , wherein the bottom and top portions of the conductive material are electrically connected.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Xue Hongyong
• Lui Sik
• Huang Terence
• Lin Ching-Kai
• Li Wenjun
• Yang Yi Chang
• Dun Jowei

Classifications

• H01L29/41766

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/66734

  Electricity · mapped topic

• H01L29/407 Primary

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic