Self-aligned contact for trench power MOSFET

Patent metadata

Field	Value
Publication number	US-9691863-B2
Application number	US-201514681887-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 8, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1. A method for fabricating a device, the method comprising:
forming a hard mask layer on top of a semiconductor substrate;
forming a gate trench by etching through portions of the hard mask layer and the semiconductor substrate underneath the portions of the hard mask layer;
etching remaining portions of the hard mask layer to form a plurality of space holders for contact structures over the semiconductor substrate on locations of the contact structures to be formed; and
depositing an insulating layer covering the space holders for the contact structures and between adjacent space holders over the semiconductor substrate prior to removing the space holders for the contact structures, wherein the insulating layer is a material that is resistant to a process that etches the space holder for the contact structure.

2. The method of claim 1 , further comprising:
forming an insulating liner along sidewalls inside the gate trench;
forming a gate electrode by filling conductive materials in the gate trench;
forming an oxide layer on top of the gate electrode; and
forming a body region and a source region.

3. The method of claim 2 , wherein the hard mask layer is a nitride or an oxide layer.

4. The method of claim 3 , wherein forming an insulating liner along sidewalls inside the gate trench includes forming a thicker portion of the insulating liner on the lower portion of the gate trench and a thinner portion of the insulating liner on the upper portion of the gate trench.

5. The method of claim 3 , wherein forming a gate electrode includes forming a bottom portion of the gate electrode in the lower portion of the gate trench and a top portion of the gate electrode in the upper portion of the gate trench.

6. The method of claim 3 , wherein the insulating layer is a nitride layer when the space holders for the contact structures made of an oxide.

7. The method of claim 2 , wherein the hard mask layer is an oxide-nitride-oxide layer.

8. A method for fabricating a device, the method comprising:
forming a hard mask layer on top of a semiconductor substrate, wherein the hard mask layer is an oxide-nitride-oxide layer;
forming a gate trench by etching through portions of the hard mask layer and the semiconductor substrate underneath the portions of the hard mask layer; and
forming a plurality of space holders for contact structures by leaving at least portions of the hard mask over the semiconductor substrate;
forming an insulating liner along sidewalls inside the gate trench;
forming a gate electrode by filling conductive materials in the gate trench;
forming an oxide layer on top of the gate electrode, wherein forming an oxide layer on top of the gate electrode includes forming a thicker portion of the oxide layer underneath the nitride layer of the hard mask layer
forming a body region and a source region;
depositing an insulating layer covering the space holders for the contact structures and between adjacent space holders over the semiconductor substrate, wherein the insulating layer is a material that is resistant to a process that etches the space holder for the contact structure.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Xue Hongyong
• Lui Sik
• Huang Terence
• Lin Ching-Kai
• Li Wenjun
• Yang Yi Chang
• Dun Jowei

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H01L29/66734

  Electricity · mapped topic

• H01L29/66727

  Electricity · mapped topic

• H01L29/41766

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic