Method of forming a self-aligned charge balanced power DMOS

Patent metadata

Field	Value
Publication number	US-8969953-B2
Application number	US-201314010333-A
Country	US
Kind code	B2
Filing date	Aug 26, 2013
Priority date	Dec 21, 2009
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

First claim

What is claimed is:

1. A method for forming a self-aligned charge balanced semiconductor device comprising:
a) forming one or more planar gates over a semiconductor substrate of a first conductivity type;
b) etching one or more deep trenches in the semiconductor substrate self-aligned to the planar gates;
c) filling said deep trenches with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the sem…

Assignees

• Alpha & Omega Semiconductor
• Alpha & Omega Semiconductor

Inventors

• Chen John
• Lee Yeeheng
• Guan Lingpeng
• Ho Moses
• Ma Wilson
• Bhalla Anup
• Yilmaz Hamza

Classifications

• H10P30/222

  Electricity · mapped topic

• H10D30/662

  Electricity · mapped topic

• H10D64/62

  Electricity · mapped topic

• H10D62/822

  Electricity · mapped topic

• H10D62/157

  Electricity · mapped topic