Apparatus and methods for through substrate via test

Patent metadata

Field	Value
Publication number	US-10629502-B2
Application number	US-201816029199-A
Country	US
Kind code	B2
Filing date	Jul 6, 2018
Priority date	Jul 15, 2008
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

First claim

What is claimed is:

1. A method of testing a memory structure, comprising:
in response to initiation of a test process, applying test signal to a first through substrate via (TSV) stack extending vertically though multiple memory die, the multiple memory die vertically stacked with one another, and each of the multiple memory die comprising multiple TSVs respectively aligned with corresponding TSVs of other memory die to form respective TSV stacks of serially connected TSVs extending through multiple memory die;
measuring a property of the TSV stack in response to the test signal.

2. The method of claim 1 , wherein applying the test signal comprises flowing at a current, and wherein measuring the property comprises measuring resistance of the first TSV stack in response to the current flow through the TSV stack.

3. The method of claim 2 , wherein applying the test signal comprises applying incremental steps of current to the first TSV stack.

4. The method of claim 2 , wherein measuring resistance of the first TSV stack in response to current flow through the first TSV stack is performed through use of at least one sense amp on one of the vertically stacked memory die.

5. The method of claim 4 , wherein a current flow through a reference resistance is coupled to the at least one sense amp.

6. The method of claim 1 , wherein applying the test signal comprises an oscillating signal, and wherein measuring the property comprises measuring the resistance-capacitance (RC) delay of the oscillating signal through the first TSV stack.

7. The method of claim 1 , further comprising;
applying test signals across multiple TSV stacks, and measuring a property of each of the multiple TSV stacks; and
comparing the measured property of a first TSV stack with the measured property of a second TSV stack.

8. The method of claim 7 , wherein the multiple TSV stacks includes at least one spare TSV stack; and wherein the method further comprises replacing the first TSV stack with a spare TSV stack in response to the comparing of the measured property.

9. The method of claim 1 , further comprising;
applying test signals across multiple TSV stacks, and measuring a property of each of the multiple TSV stacks; and
comparing the measured property of a first TSV stack with a reference value.

10. The method of claim 9 , wherein the multiple TSV stacks includes at least one spare TSV stack; and wherein the method further comprises replacing the first TSV stack with a spare TSV stack in response to the comparing of the measured property of the first TSV stack with the reference value.

11. The method of claim 1 , wherein applying the test signal is performed at least in part by a logic circuit on a logic chip coupled to the vertically stacked memory die.

12. The method of claim 11 , wherein the logic chip is stacked with the vertically stacked memory die.

13. The method of claim 1 , wherein measuring a property of the TSV stack comprises evaluating whether resistance of the TSV stack exceeds a reference value, and wherein the evaluating is based at least in part on the current flow through the TSV stack.

Assignees

• Micron Technology Inc

Inventors

• Hargan Ebrahim H
• Bunker Layne
• Dimitriu Dragos
• King Gregory A

Classifications

• G11C29/025

  in signal lines · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G01R31/2853 Primary

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title

• G01R31/2894

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title