Apparatus and methods for through substrate via test

Patent metadata

Field	Value
Publication number	US-2016233136-A1
Application number	US-201615131635-A
Country	US
Kind code	A1
Filing date	Apr 18, 2016
Priority date	Jul 15, 2008
Publication date	Aug 11, 2016
Grant date	—

Abstract

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

First claim

What is claimed is:

1 . An apparatus comprising:
a logic chip; and a plurality of memory chips, each of the plurality of memory chips comprising a TSV, the plurality of memory chips being stacked over the logic chip with each other so that the TSVs of the plurality of memory chips are electrically coupled in series with each other to provide a TSV stack; wherein the logic chip comprises a circuit, and the circuit is operable to flow a current through the TSV stack in response to initiation of a test for evaluating quality of the TSV stack.

2 . The apparatus of claim 1 , wherein the circuit uses the current flow through the TSV stack to measure resistance of the TSV stack.

3 . The apparatus of claim 1 ,
wherein each of the plurality of memory chips comprises a redundant TSV; wherein the plurality of memory chips are stacked with each other so that the redundant TSVs of memory chips are electrically coupled in series with each other to provide a redundant TSV stack.

4 . The apparatus of claim 3 , wherein the redundant TSV stack is configured to be used in place of the TSV stack when the tested TSV stack fails the quality test.

5 . The apparatus of claim 1 , wherein the circuit comprises a current source coupled with the TSV stack.

6 . A method comprising:
providing a chip stack structure comprising a logic chip and a plurality of memory chips, each of the plurality of memory chips comprising a TSV, the plurality of memory chips being stacked over the logic chip with each other so that the TSVs of the plurality of memory chips are electrically coupled in series with each other to provide a TSV stack; initiating a test on the chip stack structure to evaluate quality of the TSV stack; and in response, at least in part, to initiation of the test, causing the logic chip to flow current through the TSV stack.

7 . The method of claim 6 , further comprising evaluating whether resistance of the TSV stack exceeds a reference value, the evaluating based at least in part on the current flow through the TSV stack.

8 . The method of claim 7 ,
wherein each of the plurality of memory chips comprises a redundant TSV; wherein the plurality of memory chips are stacked with each other so that the redundant TSVs of the memory chips are electrically coupled in series with each other to provide a redundant TSV stack; and wherein the method further comprises replacing the TSV stack with the redundant TSV stack when the resistance of the TSV stack exceeds a reference value, the evaluating based at least in part on the current flowing through the TSV stack.

9 . An apparatus comprising:
a logic chip; and a plurality of memory chips, the memory chips arranged in a vertical stack with the logic chip, each of the plurality of memory chips comprising at least one TSV, the memory chips arranged in the stack with the at least one TSVs of each of the memory chips electrically coupled in series with each other to provide a TSV stack, with the TSV stack further in electrical communication with the logic chip; wherein the logic chip comprises a circuit controlling a current supply to the TSV stack, wherein the circuit is operable to induce a current to the TSV stack responsive to initiation of a test for evaluating the TSV stack.

10 . The apparatus of claim 9 , wherein each memory chip comprises multiple TSVs, and wherein the vertical stack of the logic chip and memory chips comprises multiple TSV stacks; and wherein the logic trip circuit is operable to induce a current to each TSV stack responsive to initiation of a test for evaluating the multiple TSV stacks.

11 . The apparatus of claim 9 , wherein the logic chip circuit comprises a sense amp coupled to the TSV stack, the sense amp coupled to the current supply and to a reference voltage.

12 . The apparatus of claim 10 , wherein the logic chip circuit comprises multiple sense amps, each sense amp coupled to a respective TSV stack, the sense amp coupled to the current supply and to a reference voltage.

13 . The apparatus of claim 10 , wherein the TSVs of each memory chip are each selectively connectable to a sense amp on that memory chip.

14 . The apparatus of claim 10 , wherein the multiple TSV stacks include at least one redundant TSV stack.

15 . The apparatus of claim 10 , wherein each sense amp is coupled to a respective latch.

16 . The apparatus of claim 9 , wherein the circuit controlling the current supplied to the TSV stack comprises a gate coupled to a current source.

17 . A method, comprising:
providing a chip stack structure comprising a logic chip and multiple memory chips vertically stacked relative to one another, each of the memory chips comprising a TSV, the memory chips being stacked with the logic chip so that the TSVs of the memory chips are electrically coupled with each other to provide a TSV stack; testing the characteristics of the TSV stack by causing the logic chip introduce current to the TSV stack, and evaluating a characteristic of the stack in response to the current.

18 . The method of claim 17 , wherein the evaluated characteristic comprises the resistance of the TSV stack, and wherein evaluating the characteristic comprises determining whether resistance of the TSV stack exceeds a reference value, the evaluating based at least in part on the current flow through the TSV stack.

19 . The method of claim 17 , wherein the logic chip comprises:
a gate coupled to a current source, such that causing the logic chip to introduce current to the TSV stack comprises actuating the gate to provide electrical communication between the current source and the TSV; and a sense amp coupled to the TSV.

20 . The method of claim 19 , wherein the sense amp is also coupled to a reference voltage, and wherein the logic chip further comprises a latch coupled to the sense amp.

Assignees

• Micron Technology Inc

Inventors

• Hargan Ebrahim H
• Bunker Layne
• Dimitriu Dragos
• King Gregory A

Classifications

• G11C29/816

  for an application-specific layout · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• G11C2029/5006

  Current · CPC title

• G01R31/2894

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title

• G11C29/022

  in I/O circuitry · CPC title