Apparatus and methods for through substrate via test

Patent metadata

Field	Value
Publication number	US-9318394-B2
Application number	US-201414494147-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Jul 15, 2008
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

First claim

What is claimed is:

1. A method of comparing electrical resistances, comprising:
connecting an output of an adjustable reference to a first input terminal of a sense amplifier circuit;
adjusting a level of the output by a plurality of steps of a selected size;
connecting a second input terminal of the sense amplifier circuit to at least one of a plurality of electrical paths each comprising a series connected plurality of vias;
applying a first current having a selected value to at least one of the plurality of electrical paths;
determining when the output equals a voltage on the second input terminal of the sense amplifier;
recording the level for each of the plurality of electrical paths; and
determining a quality factor proportional to the voltage on the second input terminal for each of the plurality of electrical paths.

2. The method of claim 1 , further comprising:
connecting a second current supply to the second input terminal of the sense amplifier.

3. The method of claim 2 , further comprising:
providing the second current supply as a supply with a controllable variable output value.

4. The method of claim 1 , further comprising:
adjusting the level with a control circuit.

5. The method of claim 1 , wherein adjusting the level of the output by a plurality of steps of selected size comprises adjusting a current level from 0.25 to 2.5 milliamps.

6. The method of claim 5 , wherein the steps comprise 0.25 milliamp steps.

7. The method of claim 1 , further comprising ranking the quality factor for each of the plurality of electrical paths.

8. The method of claim 7 , wherein determining the quality factor for each of the plurality of electrical paths comprises determining the quality factor relative to other electrical paths of the plurality of electrical paths.

9. A method, comprising:
connecting a plurality of integrated circuits to form a plurality of series connected electrical through substrate via stacks;
connecting a first reference to a power supply through a first resistor having a selected resistance value;
connecting a first end of a series connected electrical through substrate via stack to the first reference by a second selected resistance coupled to a first transistor having a transistor resistance value;
connecting a second end of the series connected electrical through substrate via stack to a second reference;
connecting a first end of each one of the series connected electrical through substrate via stacks through a second transistor to the first reference;
connecting a second end of each one of the series connected electrical through substrate via stacks to be measured through a first input of a sense amplifier;
connecting a second input of each sense amplifier to the second reference; and
determining a resistance of each one of the plurality of series connected electrical through silicon via stacks by measuring an output value of each sense amplifier.

10. The method of claim 9 , where the second reference is not directly connected to a power supply.

11. The method of claim 10 , wherein the second reference is connected to the power supply by a through silicon via string.

12. The method of claim 9 , where each sense amplifier is a selected sense amplifier in at least one of the plurality of integrated circuits.

13. The method of claim 9 , wherein determining the resistance of each one of the plurality of series connected electrical through silicon via stacks comprises:
repeating the determining after the plurality of integrated circuits has been operated for a selected time period in at least one of a normal operational mode, an accelerated operational mode, a static voltage stress mode, or an environmental stress mode to evaluate through silicon via string degradation and failure rates.

14. The method of claim 9 , wherein each sense amplifier is part of a memory circuit.

15. The method of claim 9 , further comprising turning on individual vias for testing.

16. The method of claim 15 , further comprising turning on the individual vias for testing by enabling via stacks with an enable transistor.

17. The method of claim 16 , further comprising connecting the first end of the series connected electrical through substrate via stack to the first reference through the enable transistor.

18. The method of claim 9 , wherein connecting the first reference to the power supply through the first resistor having the selected resistance value comprises connecting a ring oscillator through the first resistor.

Assignees

• Micron Technology Inc

Inventors

• Hargan Ebrahim H
• Bunker Layne
• Dimitriu Dragos
• King Gregory A

Classifications

• G11C2029/5006

  Current · CPC title

• G11C29/816

  for an application-specific layout · CPC title

• G11C29/025

  in signal lines · CPC title

• G01R31/2853 Primary

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title

• G11C29/022

  in I/O circuitry · CPC title