Inter-plane offset in backside contact via structures for a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-9917093-B2
Application number	US-201615195446-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jun 28, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.

First claim

What is claimed is:

1. A three-dimensional memory device comprising a plurality of planes, wherein each of the plurality of planes comprises:
a respective alternating stack of insulating layers and electrically conductive layers located over a substrate;
strings of memory stack structures, wherein each of the memory stack structures extends through the respective alternating stack and comprises a vertical stack of memory elements, a tunneling dielectric, and a vertical semiconductor channel; and
backside contact via structures vertically extending through the respective alternating stack, extending generally along a first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction that is perpendicular to the first horizontal direction,
wherein:
a first plane among the plurality of planes includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures;
a second plane among the plurality of planes is located at a position laterally shifted from a position of the first plane along the first horizontal direction and includes a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures; and
the first plurality of backside contact via structures are laterally offset with respect the second plurality of backside contact via structures along the second horizontal direction, wherein:
each of the backside contact via structures includes multiple laterally extending portions that extend along the first horizontal direction and laterally offset along the second horizontal direction and adjoined by adjoining portions that laterally extend along a direction different from the first direction; and
a first string among the strings of memory stack structures includes an outermost row of memory stack structures located along a straight line extending parallel to the first horizontal direction, wherein a region free of memory stack structures is provided between the outermost row of memory stack structures and a backside contact via structure among the backside contact via structures that is most proximal to the first string.

2. The three-dimensional memory device of claim 1 , wherein:
the first plurality of backside contact via structures are spaced apart by a backside contact via structure pitch;
the second plurality of backside contact via structures are spaced apart by the backside contact via structure pitch; and
a lateral offset distance between the first plurality of backside contact via structures and the second plurality of backside contact via structures is in a range from 10% to 90% of the backside contact via structure pitch.

3. The three-dimensional memory device of claim 1 , wherein each backside contact via structure is laterally spaced from the strings of memory stack structures by a respective insulating spacer.

4. The three-dimensional memory device of claim 1 , further comprising bit lines that are resistively connected to respective vertical semiconductor channels in the memory stack structures and laterally extending along the second horizontal direction.

5. The three-dimensional memory device of claim 1 , further comprising doped semiconductor source regions located within the substrate and electrically connected to the backside contact via structures.

6. The three-dimensional memory device of claim 1 , wherein:
each of the electrically conductive layers comprise word line strips that laterally extend generally along the first horizontal direction and laterally confined along the second horizontal direction by a pair of trenches including a pair of backside contact via structures; and
each underlying electrically conductive layer within the alternating stack extends farther along the first horizontal direction than any overlying electrically conductive layer within the alternating stack.

7. The three-dimensional memory device of claim 1 , wherein the backside contact via structure that is most proximal to the first string comprises:
a first backside contact via structure portion that is spaced from the outermost row of memory stack structures by a first distance along the second horizontal direction; and
a second backside contact via structure portion that is spaced from the outermost row of memory stack structures by a second distance along the second horizontal direction.

8. The three-dimensional memory device of claim 7 , wherein:
a first subset of at least two memory stack structures within the outermost row of memory stack structures is laterally spaced from the first backside contact via structure portion by the first distance; and
a second subset of at least two other memory stack structures within the outermost row of memory stack structures is laterally spaced from the second backside contact via structure portion by the second distance.

9. The three-dimensional memory device of claim 7 , wherein the first backside contact via structure portion and the second backside contact via structure portion are adjoined to each other by a third backside contact via structure portion that laterally extends along the second horizontal direction by a distance greater than a width of the first backside contact via structure portion.

10. The three-dimensional memory device of claim 7 , wherein the first backside contact via structure portion and the second backside contact via structure portion are adjoined to each other by a third backside contact via structure portion that laterally extends along a horizontal direction between the first horizontal direction and the second horizontal direction by a distance greater than a width of the first backside contact via structure portion.

11. The three-dimensional memory device of claim 7 , wherein the backside contact via structure that is most proximal to the first string includes at least three laterally extending portions that extend along the first horizontal direction and at least two adjoining portions that connect a neighboring pair of laterally extending portions such that the backside contact via structure that is most proximal to the first string generally extends at an oblique angle relative to the first horizontal direction.

12. The three-dimensional memory device of claim 7 , wherein the backside contact via structure that is most proximal to the first string includes at least three laterally extending portions that extend along the first horizontal direction and at least two adjoining portions that connect a neighboring pair of laterally extending portions such that the backside contact via structure that is most proximal to the first string generally extends along the first horizontal direction with periodic lateral deviations along the second horizontal direction.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the m

Assignees

• Sandisk Technologies Llc

Inventors

• Chu Cheng-Chung
• Pachamuthu Jayavel
• Pham Tuan
• Ito Fumitoshi
• Higashitani Masaaki

Classifications

• H01L27/1157

  Electricity · mapped topic

• H01L21/76802

  Electricity · mapped topic

• H01L21/22

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic