Three-dimensional memory devices containing memory block bridges

Patent metadata

Field	Value
Publication number	US-9679906-B2
Application number	US-201514823274-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Aug 11, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising a first memory block containing a plurality of memory sub-blocks located on a substrate, wherein:
each memory sub-block comprises a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures;
alternating layers comprising insulating layers and electrically conductive layers are located over the substrate;
a first portion of neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure; and
a subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks;
wherein the monolithic three-dimensional memory device further comprises:
a contact region located adjacent to a device region containing the first memory block;
a plurality of sets of stepped surfaces in the contact region located adjacent to a respective memory sub-block within the first memory block in the device region;
a first set of stepped surfaces includes a first set of vertically coincident sidewalls of a first subset of the electrically conductive layers located at a first set of levels;
a second set of stepped surfaces includes a second set of vertically coincident sidewalls of a second subset of the electrically conductive layers located at a second set of levels;
the first set of levels and the second set of levels are staggered with respect to each other; and
a block level backside contact via structure located between the first memory block and a second memory block, wherein there is no gap in the block level backside contact via structure and the alternating layers do not contiguously extend between the memory block and the second memory block.

2. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

3. The monolithic three-dimensional memory device of claim 1 , wherein:
each electrically conductive layer exposed at a top of a step in a first sets of stepped surfaces in the contact region is contacted by a respective control gate contact via structure;
the contacted electrically conductive layer extends from the first set of stepped surfaces in the contact region into the first memory block in the contact region such that the contacted electrically conductive layer is present and is electrically continuous in all memory sub-blocks in the first memory block;
the contacted electrically conductive layer in the first set of stepped surfaces in the contact region overlies one or more underlying electrically conductive in the first set of stepped surfaces;
the underlying electrically conductive layers are not contacted by the respective control gate contact via structure in the first set of stepped surfaces; and
each underlying electrically conductive layer in the first set of stepped surfaces is contacted by the respective control gate contact via structure in a different set of stepped surfaces.

4. The monolithic three-dimensional memory device of claim 1 , wherein the backside contact via structure is of unitary construction and includes a bridge portion that overlies a portion of the alternating layers that are located in the bridge region.

5. The monolithic three-dimensional memory device of claim 4 , further comprising an isolation dielectric structure comprising a dielectric material and underlying the bridge portion, wherein the isolation dielectric structure contacts sidewalls of another subset of the alternating layers that are located above the subset of the alternating layers.

6. The monolithic three-dimensional memory device of claim 5 , further comprising an insulating spacer that laterally surrounds the backside contact structure;
wherein the insulating spacer contacts sidewalls of the subset of the alternating layers and the insulating spacer contacts sidewalls of the isolation dielectric structure.

7. The monolithic three-dimensional memory device of claim 4 , further comprising at least one contact level dielectric layer overlying the alternating layers and the sets of memory stack structures;
wherein a top surface of the backside contact via structure is coplanar with a topmost surface of the at least one contact level dielectric layer; and
wherein a bottom surface of the bridge portion is located within a horizontal plane overlying a topmost surface of the alternating stack.

8. The monolithic three-dimensional memory device of claim 1 , wherein each memory stack structure extends through the alternating stack and comprises, from outside to inside:
at least one blocking dielectric,
a memory material layer,
a tunneling dielectric, and
a vertical semiconductor channel contacting an overlying drain region.

9. The monolithic three-dimensional memory device of claim 8 , further comprising a retro-stepped dielectric material portion having a sidewall that contacts a plurality of electrically conductive layers within the alternating stack, and source regions underlying the backside contact via structures and located in, or on, the substrate;
wherein a semiconductor channel contiguously extends between each drain region and one of the source regions; and
wherein backside contact via structures comprise source electrodes or source side local interconnects.

10. A monolithic three-dimensional memory device comprising a first memory block containing a plurality of memory sub-blocks located on a substrate, wherein:
each memory sub-block comprises a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures;
alternating layers comprising insulating layers and electrically conductive layers are located over the substrate;
a first portion of neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure; and
a subset of the alternating layers contiguously extends

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lu Zhenyu
• Alsmeier Johann
• Mao Daxin
• Shi Wenguang
• Koka Sateesh
• Makala Raghuveer S
• Matamis George
• Lee Yao-Sheng
• Ge Chun

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title