Multiply-accumulate circuits

Patent metadata

Field	Value
Publication number	US-10180820-B2
Application number	US-201615282021-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

First claim

The invention claimed is:

1. A multiply-accumulate circuit comprising:
a set of row driver circuits, each row driver of the row driver circuits comprising a shift register that is initialized to a ‘0’ value, wherein each row driver receives an input vector bit of an input vector;
a token propagation unit configured to propagate a ‘1’ value through the set of row driver circuits;
a set of memristor circuits linked to the set of row driver circuits, wherein each memristor stores a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation;
a sense amplifier linked to the set of memristor circuits to apply an output voltage based on a current output from a memristor of the set of memristor circuits, the current output representative of the weight value bit stored by the memristor; and
counter circuitry to store a counter value and to adjust the counter value based on a row value output from the set of row driver circuits, the output voltage of the sense amplifier, or both,
wherein a particular row is activated when the shift register of the row driver of the particular row stores a ‘1’ value.

2. The circuit of claim 1 , wherein a particular row driver and a corresponding memristor are active at a particular time; and
wherein the counter circuitry adjusts the counter value by incrementing, decrementing, or taking no action based on the row value output from the particular row driver and the output voltage applied by the sense amplifier based on the current output of the corresponding memristor circuit.

3. The circuit of claim 2 , wherein the counter circuitry is to:
increment the counter value when the input vector bit received by the particular row driver is a ‘1’ value and the corresponding memristor stores a ‘1’ value for the weight value bit;
decrement the counter value when the input vector bit received by the particular row driver is a ‘1’ value and the corresponding memristor stores a ‘0’ value for the weight value bit; and
take no action when the input vector bit received by the particular row driver is a ‘0’ value.

4. The circuit of claim 1 , wherein the counter circuitry stores the result of the multiply-accumulate operation between the input vector and the weight value after each row driver and corresponding memristor have been activated.

5. The circuit of claim 1 , wherein each memristor stores a ‘1’ value for the weight value bit when the memristor circuit is programmed to a low resistive state and stores a ‘0’ value for the weight bit when the memristor is programmed to a high resistive state.

6. The circuit of claim 5 , wherein:
the ‘0’ value for the weight value bit represents an actual weight value of ‘−1’; and
the ‘1’ value for the weight value bit represents an actual weight value of ‘1’.

7. The circuit of claim 1 , wherein each row driver comprises bypass circuitry to bypass activation of the row driver when the input vector bit received by the row driver is a ‘0’ value.

8. The circuit of claim 7 , wherein the counter circuitry stores the result of the multiply-accumulate operation between the input vector and the weight value after activation of each row driver that receives an input vector bit having a ‘1’ value and corresponding memristor.

9. The circuit of claim 1 , wherein:
a ‘0’ value for the input vector bit represents an actual input vector value of ‘−1’; and
a ‘1’ value for the input vector bit represents an actual input vector value of ‘1’; and
wherein the counter circuitry is to adjust the counter value when a particular row is activated by:
incrementing the counter value when:
both the row value output by a row driver of the particular row and the output voltage applied by the sense amplifier is a ‘0’ value; or
both the row value output by the row driver of the particular row and the output voltage applied by the sense amplifier is a ‘1’ value; and

decrementing the counter value when:
the row value output by the row driver of the particular row is a ‘0’ value and the output voltage applied by the sense amplifier is a ‘1’ value; or
the row value output by the row driver of the particular row is a ‘1’ value and the output voltage applied by the sense amplifier is a ‘0’ value.

10. A method comprising:
driving, by a row driver of a multiply-accumulate circuit, a row value onto a row value line based on an input vector bit of an input vector received by the row driver, the row driver comprising a shift register that is initialized to a ‘0’ value, and the driving by the row driver being response to the shift register storing a ‘1’ value propagated by a token propagation unit;
driving, by the row driver, a row line that controls a corresponding memristor according to the input vector bit, the corresponding memristor storing a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation;
generating, by a sense amplifier, an output voltage based on a current output from the corresponding memristor; and
adjusting, by counter circuitry, a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

11. The method of claim 10 , wherein driving the row line comprises driving the row line high when the input vector bit has a value of ‘1’ and driving the row line low when the input vector bit has a value of ‘0’.

12. The method of claim 10 , further comprising:
receiving, by the row driver, an activation token from a previous row driver in the multiply-accumulate circuit, the activation token corresponding to the ‘1’ value propagated by the token propagation unit; and
driving the row line and the row value line responsive to receiving the activation token.

13. The method of claim 10 , wherein adjusting the counter value by the counter circuitry comprises:
incrementing the counter value when the input vector bit received by the row driver is a ‘1’ value and the corresponding memristor stores a ‘1’ value for the weight value bit;
decrementing the counter value when the input vector bit received by the particular row driver is a ‘1’ value and the corresponding memristor stores a ‘0’ value for the weight value bit; and
taking no action when the input vector bit received by the particular row driver is a ‘0’ value.

14. The method of claim 10 , wherein:
a ‘0’ value for the input vector bit represents an actual input vector value of ‘−1’; and
a ‘1’ value for the input vector bit represents an actual input vector value of ‘1’; and
wherein the adjusting the counter value by the counter circuitry comprises:
incrementing the counter value when:
both the row value driven by the row driver and the output voltage generated by the sense amplifier is a ‘0’ value; or
both the row value driven by the row driver and the output voltage generated by the sense amplifier is a ‘1’ value; and

decrementing the counter value when:
the row value driven by the row driver is a ‘0’ value and the output voltage generated by the sense amplifier is a ‘1’ value; or
the row value driven by the row driver is a ‘1’ value and the output voltage generated by the sense amplifier is a ‘0’ value.

15. The method of claim 10 , wherein driving the row line according to the input vector bit comprises:
driving the row line high with a memristor read voltage when the input vector bit is a ‘1’ value and an activation token propagated through the multiply-accumulate circuit is latched by a shift register of the row driver; and
causing the row line to float otherwise.

Assignees

• Hewlett Packard Entpr Dev Lp
• Hewlett Packard Enterprlse Dev Lp

Inventors

• Buchanan Brent
• Zheng Le
• Strachan John Paul

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G06F2207/4802

  Special implementations · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title