Memristor-based adders using memristors-as-drivers (MAD) gates

Patent metadata

Field	Value
Publication number	US-9921808-B1
Application number	US-201715612942-A
Country	US
Kind code	B1
Filing date	Jun 2, 2017
Priority date	Jun 2, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

First claim

The invention claimed is:

1. A ripple carry adder, comprising:
a first memristor, wherein said first memristor is connected to a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a fourth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a fifth switch;
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to a sixth switch;
a fifth memristor connected in parallel to said fourth memristor, wherein said fifth memristor is connected to a seventh and an eighth switch, wherein said seventh and eighth switches are connected in series;
a sixth memristor connected in parallel to said fifth memristor, wherein said sixth memristor is connected to a ninth and a tenth switch, wherein said ninth and tenth switches are connected in parallel;
a seventh memristor connected in parallel to said sixth memristor, wherein said seventh memristor is connected to a first power source; and
an eighth memristor connected in parallel to said seventh memristor, wherein said eighth memristor is connected to said first power source.

2. The ripple carry adder as recited in claim 1 , wherein said first memristor is connected to a second power source via a first resistor, wherein said third switch is connected to a third power source, wherein said fifth, sixth, seventh, ninth and tenth switches are connected to a fourth power source, and wherein said third, fourth, fifth and sixth memristors are connected to a fifth power source.

3. The ripple carry adder as recited in claim 1 , wherein said first memristor is connected to a second power source via a first resistor, wherein said second switch is connected to ground via a second resistor, wherein said second memristor is connected to said ground via a third resistor, wherein said third memristor is connected to said ground via a fourth resistor, wherein said fourth memristor is connected to said ground via a fifth resistor, wherein said fifth memristor is connected to said ground via a sixth resistor, wherein said sixth memristor is connected to said ground via a seventh resistor, wherein said seventh memristor is connected to said ground via an eighth resistor, and wherein said eighth memristor is connected to said ground via a ninth resistor.

4. The ripple carry adder as recited in claim 1 , wherein an eleventh switch and a twelfth switch are connected to said seventh memristor, wherein a thirteenth switch and a fourteenth switch are connected to said eighth memristor.

5. A ripple carry adder, comprising:
a first memristor connected to a first power source, wherein said first memristor is connected to a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a second power source is connected to said third switch, wherein a fourth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a fifth switch, a sixth switch and a seventh switch, wherein said sixth and seventh switches are connected in series, wherein said sixth and seventh switches are connected in parallel to said fifth switch; and
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch, wherein said eighth, ninth and tenth switches are connected in series, wherein said eleventh and twelfth switches are connected in parallel, wherein a combination of said eleventh and twelfth switches is connected in series with said thirteenth switch, wherein a combination of said eighth, ninth and tenth switches is connected in parallel to a combination of said eleventh, twelfth and thirteenth switches.

6. The ripple carry adder as recited in claim 5 , wherein said first power source is connected to said first memristor via a first resistor, wherein said second switch is connected to ground via a second resistor, wherein said second memristor is connected to said ground via a third resistor, wherein said third memristor is connected to said ground via a fourth resistor, wherein said fourth memristor is connected to said ground via a fifth resistor.

7. The ripple carry adder as recited in claim 5 , wherein a third power source is connected to said fifth, sixth, eighth, eleventh and twelfth switches, wherein a fourth power source is connected to said third memristor.

8. A carry select adder, comprising:
a first memristor connected to a first power source, wherein said first memristor is connected to a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a second power source is connected to said third switch, wherein a fourth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a fifth switch, a sixth switch and a seventh switch, wherein said sixth and seventh switches are connected in series, wherein said sixth and seventh switches are connected in parallel to said fifth switch;
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch, wherein said eighth, ninth and tenth switches are connected in series, wherein said eleventh and twelfth switches are connected in parallel, wherein a combination of said eleventh and twelfth switches is connected in series with said thirteenth switch, wherein a combination of said eighth, ninth and tenth switches is connected in parallel to a combination of said eleventh, twelfth and thirteenth switches;
a fifth memristor connected in parallel to said fourth memristor, wherein said fifth memristor is connected to a fourteenth switch, a fifteenth switch and a sixteenth switch, wherein said fifteenth and sixteenth switches are connected in series, wherein said fifteenth and sixteenth switches are connected in parallel to said fourteenth switch; and
a sixth memristor connected in parallel to said fifth memristor, wherein said sixth memristor is connected to a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, a twenty-first switch and a twenty-second switch, wherein said seventeenth, eighteenth and nineteenth switches are connected in series, wherein said twentieth and twenty-first switches are connected in parallel, wherein a combination of said twentieth and twenty-first switches is connected in series with said twenty-second switch, wherein a combination of said seventeenth, eighteenth and nineteenth switches is connected in parallel to a combination of said twentieth, twenty-first and twenty-second switches.

9. The carry select adder as recited in claim 8 , wherein said first power source is connected to said first memristor via a first resistor, wherein said second switch is connected to ground via a second resistor, wherein said second memristor is connected to said ground via a third resistor, wherein said third memristor is connected to said ground via a fourth resistor, wherein said fourth memristor is connected to said ground via a fifth resistor, wherein said fifth memristor is connected to said ground via a sixth resistor, wherein said

Assignees

• Univ Texas

Inventors

• Swartzlander Earl
• Guckert Lauren

Classifications

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title

• G06F7/505

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/48 Primary

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title

• G06F2207/4828

  Negative resistance devices, e.g. tunnel diodes, gunn effect devices · CPC title