Memristor-based adders using memristors-as-drivers (MAD) gates

Patent metadata

Field	Value
Publication number	US-9971564-B1
Application number	US-201815887823-A
Country	US
Kind code	B1
Filing date	Feb 2, 2018
Priority date	Jun 2, 2017
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

First claim

The invention claimed is:

1. A carry lookahead adder, comprising:
a first memristor, wherein said first memristor is connected to a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch and a tenth switch, wherein said first, second, third and fourth switches are connected in series, wherein said fifth, sixth and seventh switches are connected in series, wherein said eighth and ninth switches are connected in series, wherein a combination of said first, second, third and fourth switches is connected in parallel to a combination of said fifth, sixth and seventh switches which is connected in parallel to a combination of said eighth and ninth switches which is connected in parallel to said tenth switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch and a sixteenth switch, wherein said eleventh, twelfth and thirteenth switches are connected in series, wherein said fourteenth and fifteenth switches are connected in series, wherein a combination of said eleventh, twelfth and thirteenth switches is connected in parallel to a combination of said fourteenth and fifteenth switches which is connected in parallel to said sixteenth switch; and
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a seventeenth switch, an eighteenth switch and a nineteenth switch, wherein said seventeenth and eighteenth switches are connected in series, wherein a combination of said seventeenth and eighteenth switches is connected in parallel to said nineteenth switch.

2. The carry lookahead adder as recited in claim 1 , wherein said first memristor is connected to ground via a first resistor, wherein said first memristor is connected to said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth switches via a second resistor, wherein said second memristor is connected to said ground via a third resistor, wherein said second memristor is connected to said eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth switches via a fourth resistor, wherein said third memristor is connected to said ground via fifth resistor, wherein said third memristor is connected to said seventeenth, eighteenth and nineteenth switches via a sixth resistor.

3. The carry lookahead adder as recited in claim 2 , wherein said first, fifth, eighth, tenth, eleventh, fourteenth, sixteenth, seventeenth and nineteenth switches are connected to a first power source, wherein said second, fourth and sixth resistors are connected to a second power source.

4. The carry lookahead adder as recited in claim 1 further comprising:
a first circuit comprising:
a fourth memristor connected to a twentieth switch, a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch and a twenty-fifth switch, wherein said twentieth, twenty-first, twenty-second switches are connected in series, wherein said twenty-third and twenty-fourth switches are connected in parallel, wherein a combination of said twenty-third and twenty-fourth switches is connected in series with said twenty-fifth switch, wherein a combination of said twentieth, twenty-first and twenty-second switches is connected in parallel to a combination of said twenty-third, twenty-fourth and twenty-fifth switches;

a second circuit connected in parallel to said first circuit, wherein said second circuit is configured identically to said first circuit;
a third circuit connected in parallel to said second circuit, wherein said third circuit is configured identically to said second circuit; and
a fourth circuit connected in parallel to said third circuit, wherein said fourth circuit is configured identically to said third circuit.

5. The carry lookahead adder as recited in claim 4 , wherein said fourth memristor is connected to ground via a first resistor.

6. The carry lookahead adder as recited in claim 4 , wherein a first power source is connected to said twentieth, twenty-third and twenty-fourth switches, wherein a second power source is connected to said fourth memristor.

7. A carry lookahead adder, comprising:
a first memristor connected to a first power source, wherein said first memristor is connected to a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a second power source is connected to said third switch, wherein a fourth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a fifth switch;
a fourth memristor connected in parallel to said first memristor, wherein said fourth memristor is connected to a sixth switch and a seventh switch, wherein said fourth memristor is connected to said first power source, wherein an eighth switch is connected to said third and fourth memristors;
a fifth memristor connected in parallel to said third memristor, wherein said fifth memristor is connected to a ninth switch;
a sixth memristor connected in parallel to said fourth memristor, wherein said sixth memristor is connected to a tenth switch and an eleventh switch, wherein said sixth memristor is connected to said first power source, wherein a twelfth switch is connected to said fifth and sixth memristors;
a seventh memristor connected in parallel to said fifth memristor, wherein said seventh memristor is connected to a thirteenth switch;
an eighth memristor connected in parallel to said sixth memristor, wherein said eighth memristor is connected to a fourteenth switch and a fifteenth switch, wherein said eighth memristor is connected to said first power source, wherein a sixteenth switch is connected to said seventh and eighth memristors;
a ninth memristor connected in parallel to said eighth memristor, wherein said ninth memristor is connected to a seventeenth switch, an eighteenth switch, a nineteenth switch and a twentieth switch, wherein said seventeenth, eighteenth, nineteenth and twentieth switches are connected in series; and
a tenth memristor connected in parallel to said ninth memristor, wherein said tenth memristor is connected to a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a twenty-fifth switch, a twenty-sixth switch, a twenty-seventh switch, a twenty-eighth switch, a twenty-ninth switch and a thirtieth switch, wherein said twenty-first, twenty-second, twenty-third and twenty-fourth switches are connected in series, wherein said twenty-fifth, twenty-sixth and twenty-seventh switches are connected in series, wherein said twenty-eighth and twenty-ninth switches are connected in series, wherein a combination of said twenty-first, twenty-second, twenty-third and twenty-fourth switches are connected in parallel to a combination of said twenty-fifth, twenty-sixth and twenty-seventh switches, wherein said combination of said twenty-fifth, twenty-sixth and twenty-seventh switches is connected in parallel to a combination of said twenty-eighth and twenty-ninth switches, wherein said combination of said twenty-eighth and twenty-ninth switches is connected in parallel to said thirtieth switch.

8. The carry lookahead adder as recited in claim 7 , wherein said seventeenth, twenty-first, twenty-fifth, twenty-eighth and thirtieth switches are connected to a third power source, wherein said ninth and tenth memristors are connected to a fourth power source.

9. The carry lookahead adder as recited in claim 7 , wh

Assignees

• Univ Texas

Inventors

• Swartzlander Earl
• Guckert Lauren

Classifications

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/508

  using carry look-ahead circuits · CPC title

• G06F7/505

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• G06F7/48 Primary

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title