Chip package for two-phase cooling and assembly process thereof

Patent metadata

Field	Value
Publication number	US-10607963-B2
Application number	US-201615266786-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Sep 15, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

Devices that have integrated cooling structures for two-phase cooling and methods of assembly thereof are provided. In one example, a chip manifold can be affixed to a chip. An interface can be located at a first position between the chip manifold and the manifold cap. Furthermore, the interface can create a seal.

First claim

What is claimed is:

1. A device, comprising:
a chip manifold affixed to a chip, wherein a first area of the chip manifold is less than a second area of the chip;
an interface layer at a first location between the chip manifold and a manifold cap, wherein the interface layer is a seal; and
an adhesive layer affixing the chip manifold to the chip, wherein the chip has a curved shape along an exterior boundary of the chip, and wherein the chip manifold is curved with a first curvature that is the same as a second curvature of the chip, wherein the manifold cap comprises an outlet path that surrounds the chip and the chip manifold.

2. The device of claim 1 , wherein the interface layer is further at a second location between and directly connecting the manifold cap and a substrate, and wherein the interface layer is distinct from the adhesive layer.

3. The device of claim 1 , wherein a value of thickness of the interface layer at the first location decreases as the interface layer approaches a region of the chip manifold.

4. The device of claim 1 , wherein the manifold cap has a surface facing the chip manifold.

5. The device of claim 1 , wherein the chip comprises one or more radial cooling channels traversing a surface of the chip, and the surface of the chip faces the chip manifold.

6. A device, comprising:
a chip manifold affixed to a chip, wherein a first area of the chip manifold is less than a second area of the chip;
an interface layer at a first location between the chip manifold and a manifold cap, wherein interface layer is a seal, wherein a material of the interface layer is different from a material of the manifold cap; and
an adhesive layer affixing the chip manifold to the chip, wherein the chip has a curved shape along an exterior boundary of the chip, wherein the manifold cap comprises an outlet path that surrounds the chip and the chip manifold.

7. The device of claim 6 , wherein the interface layer is further at a second location between and directly connecting the manifold cap and a substrate.

8. The device of claim 7 , wherein the interface layer is comprised of an adhesive material.

9. The device of claim 7 , wherein the interface layer is a non-adhesive seal at the first location and is comprised of an adhesive material at the second location.

10. The device of claim 6 , wherein a value of thickness of the interface layer at the first location decreases as the interface layer approaches a region of the chip manifold.

11. The device of claim 6 , wherein the manifold cap has a surface facing the chip manifold.

12. The device of claim 6 , wherein the chip comprises one or more radial cooling channels traversing a surface of the chip, and the surface of the chip faces the chip manifold.

Assignees

• IBM

Inventors

• Brunschwiler Thomas J
• Chainer Timothy Joseph
• Colgan Evan George
• Gaynes Michael Anthony
• Gelorme Jeffrey Donald
• Mcvicker Gerard
• Ozsun Ozgur
• Parida Pritish Ranjan
• Schultz Mark Delorman
• Webb Bucknell C

Classifications

• H01L2224/73253

  Electricity · mapped topic

• H01L23/433

  Electricity · mapped topic

• H01L25/0655 Primary

  Electricity · mapped topic

• H01L23/473

  Electricity · mapped topic

• H01L24/83

  Electricity · mapped topic