Memory device including a deterioration level detection circuit

Patent metadata

Field	Value
Publication number	US-10607705-B2
Application number	US-201816047384-A
Country	US
Kind code	B2
Filing date	Jul 27, 2018
Priority date	Jan 10, 2018
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

First claim

What is claimed is:

1. A memory device, comprising:
a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, wherein the selected word line and the unselected word lines are connected to a plurality of memory cells; and
a deterioration level detection circuit that detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage,
wherein the memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells,
wherein the voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

2. The memory device of claim 1 , wherein the deterioration level detection circuit determines a change of a threshold voltage of the memory cells that receive the read voltage by counting at least one of ON cells and OFF cells corresponding to the read voltage based on the data of the memory cells that receive the read voltage.

3. The memory device of claim 2 , wherein the deterioration level detection circuit detects the deterioration level based on the change of the threshold voltage of the memory cells that receive the read voltage.

4. The memory device of claim 2 , wherein the voltage generator changes the pass voltage based on the change of the threshold voltage.

5. The memory device of claim 4 , wherein the voltage generator reduces the pass voltage in response to the change of the threshold voltage.

6. The memory device of claim 1 , wherein the voltage generator sequentially provides the read voltage a plurality of times to read a bit page, and provides the pass voltage having been changed based on a prior read voltage from among a plurality of read voltages in a time section in which a posterior read voltage is applied.

7. The memory device of claim 1 , wherein the voltage generator sequentially provides the read voltage a plurality of times to read a page including a first plurality of bit pages, and provides the pass voltage having been changed based on the deterioration level detected in a prior bit page from among a second plurality of bit pages at a time of a read operation of posterior bit pages.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Han Jun
• Kim Seung Bum
• Park Il Han

Classifications

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C2029/5002

  Characteristic · CPC title