Method and system for improving error correction in data storage

Patent metadata

Field	Value
Publication number	US-9747157-B2
Application number	US-201314076165-A
Country	US
Kind code	B2
Filing date	Nov 8, 2013
Priority date	Nov 8, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method of operation of a data storage system includes: monitoring a data interface bus, the monitoring by a non-volatile memory controller; activating a zero bit counter for detecting a ratio of 1's to 0's on the data interface bus; and adjusting a threshold voltage (V th ), based on the ratio of the 1's to the 0's from the zero bit counter, by the non-volatile memory controller.

First claim

What is claimed is:

1. A method for improving error correction in a data storage system comprising:
monitoring a data interface bus that couples a non-volatile memory controller to an error correction module, the monitoring by the non-volatile memory controller;
activating a zero bit counter comprising a hardware structure distinct from the non-volatile memory controller and coupled to the data interface bus for detecting a ratio of 1's to 0's on the data interface bus;
adjusting a read threshold voltage (V th ) in one or more non-volatile memory devices, based on the ratio of the 1's to the 0's from the zero bit counter, by the non-volatile memory controller; and
reading data, from a non-volatile memory device of the one or more non-volatile memory devices, by the non-volatile memory controller using the adjusted read threshold voltage.

2. The method as claimed in claim 1 , further comprising detecting an uncorrectable error condition with respect to data read from the one or more non-volatile memory devices; wherein the adjusting of the read threshold voltage is performed to prevent a reoccurrence of the uncorrectable error condition.

3. The method as claimed in claim 1 , wherein activating the zero bit counter is in response to the error correction module detecting an uncorrectable error.

4. The method as claimed in claim 1 , further comprising:
determining an amount and direction by which to adjust the read threshold voltage;
wherein the adjusting includes adjusting the read threshold voltage in the determined direction by the determined amount.

5. The method as claimed in claim 1 , further comprising accessing a non-volatile memory device of the one or more non-volatile memory devices by the non-volatile memory controller for driving the data interface bus.

6. The method of claim 1 , wherein the one or more non-volatile memory devices are flash memory devices.

7. The method as claimed in claim 1 , further comprising accessing a non-volatile memory device of the one or more non-volatile memory devices by the non-volatile memory controller for driving the data interface bus including coupling a snoop connection to the data interface bus without adding latency between the non-volatile memory controller and the error correction module.

8. A data storage system comprising:
one or more non-volatile memory devices;
an error correction module;
a non-volatile memory controller for accessing data in the one or more non-volatile memory devices and driving a data interface bus that couples the non-volatile memory controller to the error correction module;
a zero bit counter, coupled to the data interface bus and distinct from the non-volatile memory controller, for detecting a ratio of 1's to 0's on the data interface bus; and
a read threshold voltage (V th ) adjusted by the non-volatile memory controller based on the ratio of the 1's to the 0's from the zero bit counter;
wherein the non-volatile memory controller is configured to read data from a non-volatile memory device of the one or more non-volatile memory devices using the adjusted read threshold voltage.

9. The system as claimed in claim 8 , wherein the non-volatile memory controller is configured to detect an uncorrectable error condition with respect to data read from the one or more non-volatile memory devices; wherein the read threshold voltage is adjusted to prevent a reoccurrence of the uncorrectable error condition.

10. The system as claimed in claim 8 , wherein the error correction module is configured to detect an uncorrectable error; wherein the zero bit counter is activated in response to the error correction module detecting the uncorrectable error.

11. The system as claimed in claim 8 , further comprising:
a counter interface register coupled to the zero bit counter for conveying the ratio of the 1's to the 0's accumulated from the data interface bus; and
a processor module, coupled to the counter interface register, for determining an amount and direction by which to adjust the read threshold voltage (V th );
wherein the read threshold voltage is adjusted by the non-volatile memory controller in the determined direction by the determined amount.

12. The system as claimed in claim 8 , wherein a non-volatile memory device of the one or more non-volatile memory devices is accessed by the non-volatile memory controller for driving the data interface bus.

13. The system as claimed in claim 8 ,
wherein:
the zero bit counter, coupled to the data interface bus, is coupled between the error correction module and the non-volatile memory controller.

14. The system as claimed in claim 8 , wherein a non-volatile memory device of the one or more non-volatile memory devices is coupled to and read by the non-volatile memory controller using the adjusted read threshold voltage (V th ) without an uncorrectable error correction code (ECC) error detected by the error correction module.

15. The system as claimed in claim 8 , wherein the one or more non-volatile memory devices are flash memory devices.

16. The system as claimed in claim 8 , wherein a non-volatile memory device of the one or more non-volatile memory devices is accessed by the non-volatile memory controller for driving the data interface bus and the system includes a snoop connection coupled to the data interface bus without adding latency between the non-volatile memory controller and the error correction module.

Assignees

• Sandisk Entpr Ip Llc
• Sandisk Technologies Llc

Inventors

• Ellis Robert W
• Higgins James M
• Dancho Mark

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title