Read disturb and data retention handling for NAND devices

US9612957B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9612957-B2
Application numberUS-201514668890-A
CountryUS
Kind codeB2
Filing dateMar 25, 2015
Priority dateJul 30, 2014
Publication dateApr 4, 2017
Grant dateApr 4, 2017

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Abstract

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Systems, methods, and apparatus are herein disclosed for reducing read disturb and data retention errors in FLASH memory devices designed for long lifespans, such as greater than 10 or 15 years. Read disturb errors can be reduced by maintaining a read counter stored in a volatile memory and a FASTMAP memory block of the FLASH memory. When the read counter meets a threshold, then the associated memory block can be scheduled for scrubbing. Data retentions errors can be reduced by maintaining a last-erase timestamp in metadata of each memory block of a FLASH memory. When the last-erase timestamp associated with a given memory block meets a threshold, then the memory block can be scheduled for scrubbing.

First claim

Opening claim text (preview).

What is claimed is: 1. A FLASH memory device comprising: a plurality of memory blocks each having a metadata section; a FASTMAP memory block; a read counter module comprising: a counter module that increments a read counter value when a read operation is performed on a one of the plurality of memory blocks; a backup module that periodically copies the read counter value to the FASTMAP memory block; a reset module that resets the read counter value when an erase operation is performed on the one of the memory blocks; a last-erase timestamp module that updates a last-erase timestamp in a metadata section of the one of the memory blocks every time that an erase operation is performed on the one of the memory blocks; a move and erase module comprising: a read counter scrubbing scheduler that schedules data stored in the one of the memory blocks to be moved and then the one of the memory blocks to be erased when the read counter reaches a first threshold; a last-erase timestamp scrubbing scheduler that schedules data stored in the one of the memory blocks to be moved and then the one of the memory blocks to be erased when the last-erase timestamp exceeds a second threshold. 2. The system of claim 1 , wherein the read counter is stored in a volatile memory of a read/write device coupled to the FLASH memory device. 3. The system of claim 2 , wherein the FLASH memory device is an embedded memory device integrated with the read/write device. 4. The system of claim 1 , wherein a user-space application triggers the last-erase timestamp scrubbing scheduler. 5. The system of claim 4 , wherein the user-space application determines that the last-erase timestamp exceeds the second threshold. 6. The system of claim 1 , wherein the pending scrub list is handled by an unsorted block images layer wear-leveling sub-system in a background thread. 7. A method comprising: incrementing a read counter every time that a read operation is performed on a memory block of a FLASH memory; periodically making a copy of the read counter in a FASTMAP block of the FLASH memory; wherein the read counter is stored in a volatile memory of a read/write device coupled to the FLASH memory; resetting the read counter when an erase operation is performed on the memory block; updating a last-erase timestamp whenever the memory block is erased, the updating occurring in a metadata of the memory block of the FLASH memory; and scheduling the memory block for a move and erase operation when either: the read counter reaches a read count threshold; or the last-erase timestamp reaches a last-erase threshold; and identifying an invalid read counter in the FASTMAP block and, in response, reading a default value for the read counter into the volatile memory. 8. The method of claim 7 , wherein, the default value is 0 where the memory block is a memory block that has data written to it. 9. The method of claim 8 , wherein, wherein the default value is half of the first threshold where the memory block is a memory block that has data written to it. 10. The method of claim 8 , wherein, wherein the default value is an average of the last-erase timestamp for the memory block and all other last-erase timestamps in the FLASH memory device where the memory block is a memory block that has data written to it. 11. The method of claim 7 , wherein determining if the last-erase timestamp reaches a time since a second threshold is calculated using the following relationship: last-erase timestamp+an erase time limit<a current time. 12. A non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method for reducing read disturb and data retention errors in FLASH memory, the method comprising: incrementing a read counter every time that a read operation is performed on a memory block of a FLASH memory; periodically making a copy of the read counter in a FASTMAP block of the FLASH memory; resetting the read counter when an erase operation is performed on the memory block; updating a last-erase timestamp whenever the memory block is erased, the updating occurring in a metadata of the memory block of the FLASH memory; and scheduling the memory block for a move and erase operation when either: the read counter reaches a read count threshold; or the last-erase timestamp reaches a last-erase threshold; and identifying an invalid read counter in the FASTMAP block and, in response, reading a default value for the read counter into a volatile memory. 13. The method of claim 12 , wherein the read counter is stored in a volatile memory of a read/write device coupled to the FLASH memory device. 14. The method of claim 12 , wherein, the default value is 0 where the memory block is a memory block that has data written to it. 15. The method of claim 14 , wherein, wherein the default value is half of the first threshold where the memory block is a memory block that has data written to it. 16. The method of claim 15 , wherein, wherein the default value is an average of the last-erase timestamp for the memory block and all other last-erase timestamps in the FLASH memory device where the memory block is a memory block that has data written to it. 17. A system comprising: means for incrementing a read counter every time that a read operation is performed on a memory block of a FLASH memory; means for periodically making a copy of the read counter in a FASTMAP block of the FLASH memory; means for resetting the read counter when an erase operation is performed on the memory block; means for updating a last-erase timestamp whenever the memory block is erased, the updating occurring in a metadata of the memory block of the FLASH memory; and means for scheduling the memory block for a move and erase operation when either: the read counter reaches a read count threshold; or a sum of the last-erase timestamp and an erase time limit is less than a current time.

Assignees

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Classifications

  • in block erasable memory, e.g. flash memory · CPC title

  • Reliability improvement, data loss prevention, degraded operation etc · CPC title

  • management of metadata or control data · CPC title

  • Wear leveling · CPC title

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What does patent US9612957B2 cover?
Systems, methods, and apparatus are herein disclosed for reducing read disturb and data retention errors in FLASH memory devices designed for long lifespans, such as greater than 10 or 15 years. Read disturb errors can be reduced by maintaining a read counter stored in a volatile memory and a FASTMAP memory block of the FLASH memory. When the read counter meets a threshold, then the associated …
Who is the assignee on this patent?
Qualcomm Innovation Ct Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).