State dependent sensing for wordline interference correction

Patent metadata

Field	Value
Publication number	US-9721652-B2
Application number	US-201615354446-A
Country	US
Kind code	B2
Filing date	Nov 17, 2016
Priority date	Nov 17, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory cells; and
a sense circuit configured to determine a condition of a first unselected memory cell adjacent to a selected memory cell prior to sensing for the selected memory cell;
a read circuit configured to perform for the selected memory cell a plurality of sense operations for a plurality of states, the plurality of sense operations for a particular state of the selected memory cell corresponding to different conditions of the first unselected memory cell; and
a compensation circuit configured to adjust a pass bias applied to the first unselected memory cell during each of the plurality of sense operations, the pass bias including a first pass voltage for a first condition of the first unselected memory cell during sensing for a first state, a second pass voltage for a second condition of the first unselected memory cell during sensing for the first state, and a third pass voltage for the first condition during sensing for a second state that is different from the first state, the first pass voltage is greater than the second pass voltage and the third pass voltage.

2. The apparatus of claim 1 , wherein:
the read circuit is configured to sense the selected memory cell using a first reference voltage during a first sense operation and a second sense operation for the first state;
the read circuit is configured to sense the selected memory cell using a second reference voltage during a third sense operation and a fourth sense operation for the second state, the second reference voltage is greater than the first reference voltage; and
the compensation circuit is configured to drive the first unselected memory cell with the first pass voltage for the first sense operation, the second pass voltage for the second sense operation, and the third pass voltage for the third sense operation;
the second pass voltage is less than the third pass voltage and the first pass voltage.

3. The apparatus of claim 2 , wherein:
the compensation circuit is configured to drive the first unselected memory cell with the first pass voltage while driving the selected memory cell with the first reference voltage and to drive the first unselected memory cell with the second pass voltage while driving the selected memory cell with the first reference voltage; and
the compensation circuit is configured to drive the first unselected memory cell with the third pass voltage while driving the selected memory cell with the second reference voltage.

4. The apparatus of claim 3 , wherein:
the compensation circuit is configured to drive the first unselected memory cell with the second pass voltage for the fourth sense operation while driving the selected memory cell with the second reference voltage.

5. The apparatus of claim 3 , wherein:
the compensation circuit is configured to drive the first unselected memory cell with a fourth pass voltage for the fourth sense operation while driving the selected memory cell with the second reference voltage, the fourth pass voltage is higher than the second pass voltage and lower than the third pass voltage.

6. The apparatus of claim 2 , wherein:
the sense circuit is configured to drive a set of unselected word lines not including the first unselected word line with a single pass voltage while sequentially applying the first pass voltage and the second pass voltage to the first unselected word line, the single pass voltage is less than the first pass voltage and the third pass voltage and is greater than the second pass voltage.

7. The apparatus of claim 2 , wherein:
the sense circuit is configured to store a result of the first sense operation and the third sense operation when the first unselected memory cell is in the first condition; and
the sense circuit is configured to store a result of the second sense operation and the fourth sense operation when the first unselected memory cell is in the second condition, the first condition is associated with higher threshold voltages of the first unselected memory cell than the second condition.

8. The apparatus of claim 1 , further comprising:
a plurality of NAND strings including the plurality of memory cells, the plurality of NAND strings are arranged in a three-dimensional structure;
a plurality of bit lines coupled to the plurality of NAND strings; and
a source line coupled to the plurality of NAND strings;
wherein the first unselected word line is adjacent to the select word line on a drain side of the selected word line and is programmed subsequent to the selected word line during programming.

9. An apparatus, comprising:
a plurality of memory cells;
a read circuit coupled to the plurality of memory cells, the read circuit reads a selected memory cell by using a first reference voltage for a first state and a second reference voltage for a second state, the first reference voltage is lower than the second reference voltage; and
a compensation circuit coupled to the plurality of memory cells, the compensation circuit sequentially applies to a first unselected memory cell adjacent to the selected memory cell a first set of pass voltages for a plurality of sense operations for the first state and a second set of pass voltages for a plurality of sense operations for the second state, the first set of pass voltages includes a first pass voltage that is higher than each pass voltage of the second set and includes a second pass voltage that is lower than the first pass voltage.

10. The apparatus of claim 9 , wherein:
the second set of pass voltages includes a third pass voltage, the third pass voltage is lower than the first pass voltage and higher than the second pass voltage;
the compensation circuit is configured to apply to the first unselected memory cell the first pass voltage for a first sense operation for the first state and the second pass voltage for a second sense operation for the first state; and
the compensation circuit is configured to apply to the first unselected memory cell the third pass voltage for a third sense operation for the second state.

11. The apparatus of claim 10 , wherein:
the second set of pass voltages includes the second pass voltage; and
the compensation circuit is configured to apply the second pass voltage for a fourth sense operation for the second state.

12. The apparatus of claim 10 , wherein:
the second set of pass voltages includes a fourth pass voltage; and
the compensation circuit is configured to apply the fourth pass voltage for a fourth sense operation for the second state.

13. The apparatus of claim 10 , wherein:
the read circuit is configured to respond to a request to read from the selected memory cell by reading from the first unselected memory cell;
the read circuit is configured to determine data for the selected memory cell based on the first sense operation and the third sense operation if the first unselected memory cell is in a first condition; and
the read circuit is configured to determine data for the selected memory cell based on the second sense operation and the fourth sense operation if the first unselected memory cell is in a second condition.

14. The apparatus of claim 13 , further comprising a set of data latches coupled to the first unselected memory cell and the selected memory cell, wherein:
after reading from the first unselected memory cell, the set of data latches store first data if the first unselected memory cell is in the first condition and second data if the first unselected memory cell is in the second condition;
the read circuit is configured to store a result of the first sense operation in

Assignees

• Sandisk Technologies Llc

Inventors

• Puthenthermadam Sarath
• Dutta Deepanshu

Classifications

• G11C11/5635

  Erasing circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title