Method of determining default read voltage of non-volatile memory device and method of reading data of non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9666292-B2
Application number	US-201514743311-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Aug 8, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method of determining a default read voltage of a non-volatile memory device which includes a plurality of first memory cells, each of which stores a plurality of data bits as one of a plurality of threshold voltages corresponding to a plurality of logic states, includes programming a first data to the first memory cells so that the logic states of the first memory cells are balanced or equally used. The method includes applying a first default read voltage included in default read voltages to word lines coupled to the first memory cells, and measuring a first ratio of first on-cells, each of which has a threshold voltage smaller than or equal to the first default read voltage, among the first memory cells, and modifying the first default read voltage based on the first ratio and a first reference value corresponding to the first default read voltage.

First claim

What is claimed is:

1. A method of determining a default read voltage of a non-volatile memory device which includes a plurality of first memory cells, each of which is configured to store a plurality of data bits as one of a plurality of threshold voltages corresponding to a plurality of logic states, the method comprising:
programming a first data to the first memory cells so that each of the logic states are programmed into the first memory cells an equal number of times;
applying a first default read voltage from among a plurality of default read voltages to word lines coupled to the first memory cells, and measuring a first ratio of first on-cells, each of which has a threshold voltage smaller than or equal to the first default read voltage, among the first memory cells; and
modifying the first default read voltage based on the first ratio and a first reference value corresponding to the first default read voltage.

2. The method of claim 1 , wherein the first reference value is a ratio of second on-cells, each of which has a threshold voltage smaller than or equal to the first default read voltage, among the first memory cells when the first default read voltage is applied to the word lines and threshold voltages of the first memory cells are not scattered.

3. The method of claim 1 , wherein the modifying the first default read voltage based on the first ratio and the first reference value corresponding to the first default read voltage comprises decreasing the first default read voltage when the first ratio is bigger than the first reference value.

4. The method of claim 1 , wherein the modifying the first default read voltage based on the first ratio and the first reference value corresponding to the first default read voltage comprises increasing the first default read voltage when the first ratio is smaller than the first reference value.

5. The method of claim 1 , further comprising:
applying a second default read voltage from among the plurality of default read voltages to the word lines, and measuring a second ratio of second on-cells, each of which has a threshold voltage smaller than or equal to the second default read voltage, among the first memory cells; and
modifying the second default read voltage based on the second ratio and a second reference value corresponding to the second default read voltage.

6. The method of claim 1 , wherein the non-volatile memory device further comprises a plurality of second memory cells, each of which is configured to store a plurality of data bits as one of the threshold voltages corresponding to the logic states.

7. The method of claim 6 , further comprising:
programming a second data to the second memory cells so that each of the logic states are programmed into the second memory cells an equal number of times;
applying a second default read voltage from among the plurality of default read voltages to word lines coupled to the second memory cells, and measuring a second ratio of second on-cells, each of which has a threshold voltage smaller than or equal to the second default read voltage, among the second memory cells; and
modifying the second default read voltage based on the second ratio and a second reference value corresponding to the second default read voltage,
wherein a level of the first default read voltage is the same as a level of the second default read voltage, and a level of the modified first default read voltage is different from a level of the modified second default read voltage.

8. A method of reading data of a non-volatile memory device which includes a plurality of memory cells, each of which is configured to store a plurality of data bits as one of a plurality of threshold voltages corresponding to a plurality of logic states, the method comprising:
programming a first data to the memory cells so that each of the logic states are programmed into the memory cells an equal number of times;
reading a data stored in the memory cells as a second data based on default read voltages;
applying a first default read voltage from among the default read voltages to word lines coupled to the memory cells, and measuring a first ratio of first on-cells, each of which has a threshold voltage smaller than or equal to the first default read voltage, among the memory cells;
attempting to correct errors included in the second data based on an error correction code;
outputting the first data corrected from the second data as a read data of the memory cells when correction of the errors included in the second data succeeds; and
modifying the first default read voltage based on the first ratio and a first reference value corresponding to the first default read voltage and reading the data stored in the memory cells as a third data based on the default read voltages including the modified first default read voltages when correction of the errors included in the second data fails.

9. The method of claim 8 , further comprising:
attempting to correct errors included in the third data based on the error correction code;
outputting the first data corrected from the third data as the read data of the memory cells when correction of the errors included in the third data succeeds; and
reading another data stored in the memory cells based on the default read voltages including the modified first default read voltage when correction of the errors included in the third data succeeds.

10. The method of claim 9 , further comprising, when correction of the errors included in the third data fails, re-modifying the first default read voltage and reading the data stored in the memory cell as the third data based on the default read voltages including the re-modified first default read voltage until correction of the errors included in the third data succeeds.

11. The method of claim 9 , further comprising, when correction of the errors from among the third data fails, applying a second default read voltage included in the default read voltages to the word lines, measuring a second ratio of second on-cells, each of which has a threshold voltage smaller than or equal to the second default read voltage, among the memory cells, modifying the second default read voltage based on the second ratio and a second reference value corresponding to the second default read voltage, and reading the data stored in the memory cell as the third data based on the default read voltages including the modified second default read voltage.

12. The method of claim 8 , wherein the reading the data stored in the memory cells as the second data based on the default read voltages and the applying the first default read voltage from among the default read voltages to the word lines coupled to the memory cells are performed simultaneously.

13. A non-volatile memory device comprising:
a memory cell array including a plurality of first memory cells each configured to store a plurality of data bits as one of a plurality of threshold voltages corresponding to a plurality of logic states;
a control circuit configured to generate a row address signal and a column address signal based on a command signal and an address signal;
a voltage generation circuit configured to generate a first default read voltage based on a first default read voltage control signal;
an address decoder configured to apply the first default read voltage to a first word line corresponding to the row address signal when the command signal is a read command signal of the first memory cells; and
a data I/O circuit including a page buffer configured to receive a data stored in memory cells coupled to the first word line through a plurality of bit lines in response to the c

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Ryun

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title