Conformal 3D non-planar multi-layer circuitry

Patent metadata

Field	Value
Publication number	US-10568204-B2
Application number	US-201815876552-A
Country	US
Kind code	B2
Filing date	Jan 22, 2018
Priority date	Aug 9, 2012
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited. Microvias may provide electrical connections between circuit layers.

First claim

What is claimed is:

1. A conformal non-planar multi-layer circuit, comprising:
a substrate having a first non-planar surface;
a conformal circuitry layer over the substrate, the conformal circuitry layer conforming to the first non-planar surface of the substrate, and the conformal circuitry layer having a second non-planar surface;
a first conformal dielectric layer over the substrate,
wherein the first conformal dielectric layer conforms to the second non-planar surface of the substrate,
wherein the first conformal dielectric layer has a third non-planar surface, and
wherein the first conformal dielectric layer includes at least one micro via exposing the conformal circuitry layer; and

a copper circuitry layer over the conformal circuitry layer, the copper circuitry layer conforming to the third non-planar surface of the first conformal dielectric layer, and the copper circuitry layer having a fourth non-planar surface, wherein the copper circuitry layer contacts the conformal circuitry layer through the at least one micro via.

2. The conformal non-planar multi-layer circuit of claim 1 , further comprising:
a second conformal dielectric layer over the copper circuitry layer, the second conformal dielectric layer conforming to the fourth non-planar surface of the copper circuitry layer, and the second conformal dielectric layer having a fifth non-planar surface.

3. The conformal non-planar multi-layer circuit of claim 2 , wherein the second conformal dielectric layer has a thickness of about 2 mils.

4. The conformal non-planar multi-layer circuit of claim 1 , wherein the conformal circuitry layer includes a chromium-copper alloy layer.

5. The conformal non-planar multi-layer circuit of claim 4 , wherein the chromium-copper alloy layer has a thickness of about 1 micron.

6. The conformal non-planar multi-layer circuit of claim 1 , wherein the copper circuitry layer includes a chromium-copper alloy layer.

7. The conformal non-planar multi-layer circuit of claim 1 , wherein at least one of the conformal circuitry layer and the copper circuitry layer has a thickness of about 12.7 microns.

8. A method of forming a multi-layer circuit, comprising:
providing a substrate having a first non-planar surface;
forming a conformal circuitry layer over the substrate, the conformal circuitry layer conforming to the first non-planar surface of the substrate, and the conformal circuitry layer having a second non-planar surface;
depositing a first conformal dielectric layer over the conformal circuitry layer, the first conformal dielectric layer conforming to the second non-planar surface of the substrate, the first conformal dielectric layer having a third non-planar surface, and the first conformal dielectric layer including at least one micro via exposing the conformal circuitry layer; and
forming a copper circuitry layer over the conformal circuitry layer, the copper circuitry layer conforming to the third non-planar surface of the first conformal dielectric layer, the copper circuitry layer having a fourth non-planar surface, and the copper circuitry layer contacting the conformal circuitry layer through the at least one micro via.

9. The method of claim 8 , further comprising:
depositing a second conformal dielectric layer over the copper circuitry layer, the second conformal dielectric layer conforming to the fourth non-planar surface of the copper circuitry layer, and the second conformal dielectric layer having a fifth non-planar surface.

10. The method of claim 9 , wherein the depositing the second conformal dielectric layer includes performing a vapor deposition process until the second conformal dielectric layer has a thickness of about 2 mils.

11. The method of claim 8 , wherein the forming of the conformal circuitry layer includes sputtering or electroplating a chromium-copper alloy layer over the substrate.

12. The method of claim 11 , wherein the chromium-copper alloy layer has a thickness of about 1 micron.

13. The method of claim 8 , wherein the forming of the copper circuitry layer includes sputtering or electroplating a chromium-copper alloy layer over the conformal circuitry layer.

14. The method of claim 8 , wherein at least one of the conformal circuitry layer and the copper circuitry layer has a thickness of about 12.7 microns.

Assignees

• Lockheed Corp

Inventors

• Gonya Stephen
• Twigg Kenn
• Patterson Jim

Classifications

• H05K1/0284

  Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014) · CPC title

• H05K2203/0315

  Oxidising metal · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/053

  the metal substrate being covered by an inorganic insulating layer · CPC title

• H05K1/09

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title