Probability-based optimization of system on chip (SOC) power

Patent metadata

Field	Value
Publication number	US-10560116-B2
Application number	US-201715854222-A
Country	US
Kind code	B2
Filing date	Dec 26, 2017
Priority date	Dec 26, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.

First claim

What is claimed is:

1. A method of designing a system on chip (SoC), comprising:
for a total number of bits N of the SoC, calculating a minimum number of bits N P of the total number of bits N that can simultaneously switch states without producing an error across a complete warranty time period of the SoC;
carrying out power estimation calculations for the SoC using the calculated minimum number of bits N P ; and
providing a power consumption value for the SoC based on an average power value for the minimum number of bits N P , to allow configuration of a power supply to be used in a system employing the SoC.

2. The method of claim 1 and wherein the calculated minimum number of bits N P is less than or equal to N.

3. The method of claim 1 and wherein the carrying out the power estimation calculations for the total number of bits N for the SoC comprises carrying out steady state current and steady state power calculations for the SoC using the total number of bits N.

4. The method of claim 3 and wherein the carrying out the power estimation calculations for the SoC further comprises carrying out switching current and switching power calculations for the SoC using the calculated minimum number of bits N P .

5. The method of claim 1 and wherein the calculating the minimum number of bits N P comprises calculating a probability of different ones of the total number of bits N switching simultaneously.

6. The method of claim 1 and further comprising incorporating an error correction mechanism into the SoC, wherein the error correction mechanism employs at least one error correction bit.

7. The method of claim 6 and wherein the calculating the minimum number of bits N P is carried out as a function of a probability of different ones of the total number of bits N switching simultaneously and as a function of the at least one error correction bit.

8. A method comprising:
determining a number of channels to be employed in a system on chip (SoC), each channel of the number of channels including a number of bits per channel;
determining a total number of bits N for the SoC based on the number of channels and based on the number of bits per channel;
receiving warranty information for the SoC;
calculating, based on the total number of bits N and the warranty information, a minimum number of bits N P of the total number of bits N that can simultaneously switch states without producing an error across a complete warranty time period of the SoC; and
providing a power consumption value for the SoC based on a current consumption of the minimum number of bits N P that can simultaneously switch states without producing an error across the complete warranty time period of the SoC, to allow configuration of a power supply to be employed in a system employing the SoC.

9. The method of claim 8 and further comprising carrying out power estimation calculations for the SoC using the calculated minimum number of bits N P .

10. The method of claim 8 and wherein the calculated minimum number of bits N P is less than or equal to N.

11. The method of claim 9 and wherein the carrying out the power estimation calculations for the SoC comprises carrying out steady state current and steady state power calculations for the SoC using the total number of bits N.

12. The method of claim 11 and wherein the carrying out the power estimation calculations for the SoC further comprises carrying out switching current and switching power calculations for the SoC using the calculated minimum number of bits N P .

13. The method of claim 8 and wherein the calculating the minimum number of bits N P comprises calculating a probability of different ones of the total number of bits N switching states simultaneously.

14. The method of claim 8 and further comprising incorporating an error correction mechanism into the SoC, wherein the error correction mechanism employs one error correction bit thereof configured as an input to find a back to back error probability.

15. The method of claim 14 and wherein the calculating the minimum number of bits N P is carried out as a function of a probability of different ones of the total number of bits N switching states simultaneously and as a function of the one error correction bit configured as an input to find a back to back error probability.

16. A non-transitory computer-readable storage medium having encoded therein computer-executable instructions for causing a computing system programmed thereby to perform a method comprising:
for a system on chip (SoC) having a total number of bits N, calculating a minimum number of bits N P of the total number of bits N that can simultaneously switch states without producing an error across a complete warranty time period of the SoC;
carrying out power estimation calculations for the SoC using the calculated minimum number of bits N P ; and
setting an average power value for the SoC based on an average power value for the minimum number of bits N P ; and
providing a power consumption value for the SoC based on the average power value for the minimum number of bits N P , to allow configuration of a power supply to be used in a system employing the SoC.

17. The computer-readable storage medium of claim 16 and wherein the calculated minimum number of bits N P is less than or equal to N.

18. The computer-readable storage medium of claim 16 and wherein the carrying out the power estimation calculations for the SoC comprises carrying out steady state current and steady state power calculations for the SoC using the total number of bits N.

19. The computer-readable storage medium of claim 18 and wherein the carrying out the power estimation calculations for the SoC further comprises carrying out switching current and switching power calculations for the SoC using the calculated minimum number of bits N P .

20. The computer-readable storage medium of claim 16 and wherein the calculating the minimum number of bits N P comprises calculating a probability of different ones of the number of bits N switching states simultaneously.

Assignees

• Seagate Technology Llc

Inventors

• Chhabra Nitin Kumar
• Halba Rohit
• Shaw Shashi Kumar
• Mehetre Shrikrishna Nana

Classifications

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04L25/49

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title

• H03M5/16

  the pulses having three levels · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• H03K19/017509

  Interface arrangements · CPC title