Methods and systems for chip-to-chip communication with reduced simultaneous switching noise

Patent metadata

Field	Value
Publication number	US-9686107-B2
Application number	US-201615169446-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	May 20, 2010
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

First claim

We claim:

1. An apparatus comprising:
an encoder configured to receive a set of n bits, wherein n is a predetermined integer greater than or equal to 3, and to encode the set of n bits to a vector signaling code word as transitions from a previously transmitted vector signaling code word having a plurality of elements of three or more levels in the transmission interface, wherein the encoder is configured to check less than n bits of set of n bits for a first logic condition that if satisfied, configures the encoder to transition a level of a single element of the previously transmitted vector signaling code word according to a first transition-limiting function operating on a prior state of the level of the single element, and if the first logic condition fails, the encoder is configured to check less than n bits of the set of n bits for a second logic condition that if satisfied, configures the encoder to transition levels of two elements of the previously transmitted vector signaling code word according to a second transition-limiting function operating on prior states of the levels of the two elements; and
an output driver circuit configured to provide the vector signaling codeword in one transmission interval on a multi-wire bus.

2. The apparatus of claim 1 , wherein the multi-wire bus comprises n wires, and wherein the vector signaling code word comprises n elements.

3. The apparatus of claim 1 , wherein the encoder is configured to implement the first and second transition-limiting functions using a lookup table.

4. The apparatus of claim 1 , wherein the output driver circuit is a ternary driver circuit, the multi-wire bus comprises a first wire, a second wire, and a third wire, and wherein the encoder is configured to:
receive three input bits at an input and to obtain prior output states of the wires of the ternary driver circuit, the three input bits comprising a first bit, a second bit, and a third bit;
determine, for the first logic condition, that the second and the third bits of the three input bits are not both ones, and to responsively select an output wire based on the second and the third bits, and to determine a new output state of the selected wire according to the first transition-limiting function operating on the a prior state of the level of the selected wire and the first input bit; and
determine, for the second logic condition that the first bit is zero, and to responsively determine new output states of the first wire and the second wire according to the second transition-limiting function operating on prior states of levels of the first and second wires, respectively.

5. The apparatus of claim 4 , wherein the encoder is configured to select the output wire based on the index of the wire as determined by a sum of the second bit and two times the third bit.

6. The apparatus of claim 5 , wherein the encoder is configured to select the new output state based on a modulo-3 summation.

7. The apparatus of claim 1 , wherein the output driver circuit is a quaternary driver circuit, the multi-wire bus comprises a first wire, a second wire, a third wire, and a fourth wire, and wherein the encoder is configured to:
receive four input bits at an input, the four input bits comprising a first bit, a second bit, a third bit, and a fourth bit and to obtain prior output states of the quaternary driver circuit;
determine, for the first logic condition, that the fourth bit is a zero;
select, for the first transition-limiting function, from the multi-wire bus, an output wire based on the first bit and the second bit, and to select a new output state of the selected wire based on a prior state of a level of the selected wire and the third bit;
determine, for the second logic condition, that the second and third bits are not both ones, and to responsively select a pair of wires, wherein a first wire of the pair is selected according to a corresponding index determined by a combination of the first and third bits, and wherein a second wire of the pair is selected according an index determined by the first, second, and third bits, the encoder configured to determine new output states for the pair of wires according to the second transition-limiting function operating on previous states of levels of the first and second wires of the selected pair of wires, respectively; and
in response to determining that the first and second logic conditions fail, the encoder is configured to determine, for a third logic condition, that the first bit is a zero, and to responsively determine new output states of the first wire, the second wire, and the third wire, wherein the new output states are determined according to the second transition-limiting function operating on prior states of levels of the first wire, the second wire, and the third wire, respectively.

8. The apparatus of claim 7 , wherein the encoder is configured to select the output wire based on the index of the wire as determined by a sum of the first bit and two times the second bit.

9. The apparatus of claim 8 , wherein the encoder is configured to determine the new output state of the selected wire based on a modulo-3 summation.

10. The apparatus of claim 1 , further comprising a state memory circuit configured to provide the previously transmitted vector signaling code word to the encoder.

11. A method comprising:
receiving a set of n bits, wherein n is a predetermined integer greater than or equal to 3;
encoding the set of n bits into a vector signaling codeword as transitions from a previously transmitted vector signaling codeword comprising a plurality of elements of three or more values, wherein the encoding comprises checking one or more bits for a first logic condition that if satisfied, transitions a value of a single element of the previously transmitted vector signaling codeword according to a first transition-limiting function operating on a prior state of the value of the single element, and if the first logic condition fails, checking less than n bits for a second logic condition that if satisfied, transitions values of two elements of the previously transmitted vector signaling codeword according to a second transition-limiting function operating on prior states of the levels of the two elements; and
transmitting the vector signaling code word in one transmission interval on a set of wires.

12. The method of claim 11 , wherein the set of wires comprises n wires, and wherein the vector signaling code word comprises n elements.

13. The method of claim 11 , wherein the first and second transition-limiting functions are implemented using a lookup table.

14. The method of claim 11 , wherein:
encoding comprises receiving three input bits comprising a first bit, a second bit, and a third bit, and obtaining prior output states of a ternary driver circuit configured to drive the set of wires comprising a first wire, a second wire, and a third wire;
the first logic condition comprises determining that the second bit and the third bit are not both ones;
the first transition-limiting function comprises selecting an output wire based on the second and the third bit, and determining a new output state of the selected wire according to the first transition-limiting function operating on a prior state of a value of the selected wire and the first input bit;
the second logic condition comprises determining that the first bit is a zero; and
the second transition-limiting function comprises determining new output states of the first wire and the second wire, wherein the new output states are determined according to the second transition-limiting function operating on prior states

Assignees

• Kandou Labs SA

Inventors

• Fox John
• Holden Brian
• Hunt Peter
• Keay John D
• Shokrollahi Amin
• Simpson Richard
• Singh Anant
• Stewart Andrew Kevin John
• Surace Giuseppe

Classifications

• H04L25/493

  by transition coding, i.e. the time-position or direction of a transition being encoded before transmission · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H03M5/20

  the pulses having more than three levels · CPC title

• G06F13/426

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

• H03M5/16

  the pulses having three levels · CPC title