Methods and systems for chip-to-chip communication with reduced simultaneous switching noise

Patent metadata

Field	Value
Publication number	US-9357036-B2
Application number	US-201514842511-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	May 20, 2010
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

First claim

We claim:

1. A method comprising:
receiving a set of input bits representing information;
mapping, using an encoder, values to a set of wires, the values corresponding to elements of a transmit codeword of a vector signaling code, wherein at least one value is mapped by assigning the value to a corresponding wire having a wire position index determined by a logical combination of at least two of the input bits; and,
transmitting, using a plurality of line drivers, the values on the set of wires.

2. The method of claim 1 , wherein the at least one value is selected from a set of values based on a subset of the input bits.

3. The method of claim 1 , wherein the vector signaling code is a H4P code.

4. The method of claim 1 , wherein the vector signaling code is a 4b4wT code.

5. The method of claim 1 , wherein the vector signaling code is a 4b4wQ code.

6. The method of claim 1 , wherein the vector signaling code is a 2b2wT code.

7. The method of claim 1 , wherein the vector signaling code is a P4P code.

8. The method of claim 1 , wherein the vector signaling code is a P2P code.

9. The method of claim 1 , further comprising:
receiving the values on the set of wires;
forming, using a plurality of averagers, a plurality of averages based on the received values; and,
forming, using a plurality of comparators, a plurality of comparator output bits based on comparisons of the plurality of averages.

10. The method of claim 9 , wherein the comparators are multi-input comparators.

11. The method of claim 9 , wherein the comparators are simple two-input comparators.

12. The method of claim 9 , wherein the plurality of comparator output bits represents the set of input bits.

13. The method of claim 9 , further comprising forming a set of output bits based on the plurality of comparator output bits, the set of output bits representing the set of input bits.

14. An apparatus comprising:
an encoder configured to receive a set of input bits and to responsively map values to a set of wires, the values corresponding to elements of a transmit codeword of a vector signaling code, wherein at least one value is mapped by assigning the value to a corresponding wire having a wire position index determined by a logical combination of at least two of the input bits; and,
a plurality of line drivers to transmit the values on the set of wires.

15. The apparatus of claim 14 , wherein the value is selected from a set of values, the selection determined by a subset of the set of input bits.

16. The apparatus of claim 15 , wherein the vector signaling code is selected from the group consisting of a H4P code, a 4b4wT code, a 4b4wQ code, a 2b2wT code, a P4P code, and a P2P code.

17. The apparatus of claim 14 , wherein the encoder comprises combinatorial logic components configured to determine the logical combination.

18. The apparatus of claim 14 , further comprising:
a plurality of averagers configured to receive the values and to generate a plurality of averages based on the received elements; and,
a plurality of comparators configured to generate a plurality of comparator output bits based on comparisons of the plurality of averages.

19. The apparatus of claim 18 , further comprising a combinatorial logic decoder configured to generate a set of output bits based on the plurality of comparator output bits, the set of output bits representing the set of input bits.

20. The apparatus of claim 18 , wherein the comparator output bits represent the set of input bits.

Assignees

• Kandou Labs SA

Inventors

• Fox John
• Holden Brian
• Hunt Peter
• Keay John D
• Shokrollahi Amin
• Simpson Richard
• Singh Anant
• Stewart Andrew Kevin John
• Surace Giuseppe

Classifications

• G06F13/426

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

• H04L25/493

  by transition coding, i.e. the time-position or direction of a transition being encoded before transmission · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/4906 Primary

  using binary codes · CPC title

• H04L69/04 Primary

  Protocols for data compression, e.g. ROHC · CPC title