Methods and systems for energy-efficient communications interface

Patent metadata

Field	Value
Publication number	US-9362962-B2
Application number	US-201314014082-A
Country	US
Kind code	B2
Filing date	Aug 29, 2013
Priority date	May 20, 2010
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

In a high-impedance communications interface, driver energy consumption is proportional to the number of signal transitions. For signals having three or more distinct levels, it is possible for a signal driver to salvage energy from some downward signal transitions and reuse it on some subsequent upward signal transitions. To facilitate this energy-conserving behavior, communication is performed using group signaling over sets of wires using a vector signaling code, with the design and use of the vector signaling code insuring that energy availability is balanced with energy demand.

First claim

We claim:

1. A system for interconnection of two or more integrated circuit devices using a vector signaling code to communicate binary data, the system comprising:
a collection of interconnection wires connecting the two or more integrated circuit devices, the wires representing an essentially capacitive load;
a transmission interface to the collection of interconnection wires in at least one of the integrated circuit devices;
an encoder configured to receive the binary data and to responsively generate a vector signaling code word of three or more levels in the transmission interface;
a transmit driver configured to communicate the vector signaling code word from the transmission interface as three or more signal levels, the three or more signal levels comprising ‘+’, ‘0’, and ‘−’ levels on the interconnection wires, the transmit driver comprising:
transistors connected to supply voltages, the transistors configured to source and sink current to and from the essentially capacitive load of a corresponding wire during transitions from ‘0’ to ‘+’ and ‘0’ to ‘−’, respectively; and
a storage element configured to store charge from the essentially capacitive load of a first wire during a first transition from a ‘+’ to a ‘0’, and in a subsequent transition on a second wire from a ‘−’ to a ‘0,’ the storage element configured to source current to charge the essentially capacitive load of the second wire to a ‘0’.

2. The system of claim 1 , wherein the stored charge is obtained from transitions between extreme signal levels and intermediate signal levels appearing in the same or previous transmission intervals on one or more wires of the collection of interconnection wires.

3. The system of claim 2 , wherein the stored charge is controlled by constraints placed on encoding of the binary data to a vector signaling code word.

4. The system of claim 1 , wherein the transmission interface maintains a history of internal state.

5. The system of claim 1 , wherein the vector signaling code is a permutation code.

6. The system of claim 1 , wherein the encoder communicates changes of the binary data, and the transmission interface maintains a history of internal state encompassing at least one previous transmission interval.

7. The system of claim 6 , wherein the encoder comprises a variable rate communications channel for the binary data.

8. The system of claim 7 , wherein said variable rate encoder operates by the use of a protocol escape value followed by a corrective sequence.

9. A method for communication of binary data using a vector signaling code between a transmitting integrated circuit device and at least one receiving integrated circuit device, the method comprising:
encoding the binary data as a vector signaling code word comprising symbols having three or more values, the three or more values comprising a high value (‘+’), a middle value (‘0’), and a low value (‘−’);
transmitting the vector signaling code word as signal levels in one transmission interval on a set of wires, wherein a transition from a ‘−’ to a ‘0’ on a second wire uses energy stored within a storage element, the stored energy recovered from an essentially capacitive load associated with a first wire during a transition from a ‘+’ to a ‘0’ in a prior transmission interval.

10. The method of claim 9 , wherein the stored energy is controlled by constraints placed on the encoding.

11. The method of claim 10 , wherein the constraints limit allowable changes between a previous code word and a present code word.

12. The method of claim 11 , wherein the constraints depend on a history of previous signal level transmissions.

13. The method of claim 12 , wherein encoding comprises a first conversion of the binary data into a canonical form and a second conversion of the canonical form into the vector signaling code word incorporating the constraints limiting allowable changes between the previous code word and the present code word.

14. The method of claim 12 , wherein encoding and transmitting comprise a variable rate communications channel for the binary data.

15. The method of claim 14 , where said variable rate communications channel operates by the use of a protocol escape value and corrective sequence.

16. A method comprising:
receiving a set of signals representing binary input data;
encoding the set of signals into symbols of a vector signaling code word, wherein each symbol is represented at least as one of a high level (‘+’), a medium level (‘0’), or a low level (‘−’);
transmitting the symbols of the vector signaling code word over a plurality of wires, each of the wires representing an essentially capacitive load;
sourcing and sinking charge from supply voltages, using transistors, to the essentially capacitive load of a corresponding wire on transitions from ‘0’ to ‘+’ and from ‘0’ to ‘−’, respectively;
storing charge from the essentially capacitive load of a first wire in a storage element during a first transition from a ‘+’ to a ‘0’; and,
in a subsequent transition on a second wire from a ‘−’ to a ‘0,’ sourcing current from the storage element to charge the essentially capacitive load of the second wire to a ‘0’.

17. The method of claim 16 , wherein the storage element is a capacitor.

18. The method of claim 17 , wherein the capacitor has a capacitance at least 10× larger than a capacitance of the capacitive load.

19. The method of claim 16 , wherein the storage element is selected from the group consisting of an on chip element and an external device.

20. The method of claim 16 , wherein symbol transitions on the plurality of wires are controlled by constraints placed on the encoding of the binary input data to symbols of a vector signaling code word.

Assignees

• Kandou Labs SA

Inventors

• Simpson Richard
• Stewart Andrew Kevin John
• Holden Brian
• Shokrollahi Amin

Classifications

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• H04B1/06 Primary

  Receivers · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title