Non-volatile memory devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-10559577-B2
Application number	US-201815914168-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	Aug 24, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate;
a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate, the upper substrate including
a first upper substrate on the first semiconductor layer,
a first layer on the first upper substrate, and
a second upper substrate on the first layer; and

a contact, the contact extending through a portion of the first semiconductor layer to contact a bottom surface of the first upper substrate to be electrically connected to the first upper substrate, the contact configured to transfer a voltage to the first upper substrate based on an operation signal being applied to the memory cell array.

2. The non-volatile memory device of claim 1 , wherein
the first layer includes a dielectric layer, and
the non-volatile memory device further includes a capacitor, the capacitor including the first upper substrate, the second upper substrate, and the first layer.

3. The non-volatile memory device of claim 1 , wherein
the first upper substrate includes one or more insulation layers, and
the first upper substrate includes a first section and a second section, the first section and the second section separated by the one or more insulation layers.

4. The non-volatile memory device of claim 3 , further comprising:
a first contact, the first contact electrically connected to the first section, the first contact configured to transfer a first voltage to the first section based on a first operation signal associated with a first operation of the memory cell array being applied to the memory cell array; and
a second contact, the second contact electrically connected to the second section, the second contact configured to transfer a second voltage to the second section based on a second operation signal associated with a second operation of the memory cell array being applied to the memory cell array, the second voltage having a different magnitude than a magnitude of the first voltage,
wherein the contact is one of the first contact or the second contact.

5. The non-volatile memory device of claim 1 , wherein
the first upper substrate and the second upper substrate are doped with an impurity of a first conductivity type, and
the first layer is doped with an impurity of a second conductivity type, and
the second conductivity type is opposite to the first conductivity type.

6. The non-volatile memory device of claim 1 , wherein the non-volatile memory device is configured to apply a ground voltage to the first upper substrate based on an operation signal associated with an operation of the memory cell array being applied to the second upper substrate.

7. The non-volatile memory device of claim 6 , wherein the non-volatile memory device is configured to apply a voltage to the first layer based on the operation signal associated with the operation of the memory cell array being applied to the second upper substrate, the voltage having a magnitude greater than or equal to a magnitude of the ground voltage.

8. The non-volatile memory device of claim 1 , wherein
the second upper substrate is doped with an impurity of a first conductivity type, and
the second upper substrate includes a first well region and a second well region, the first well region occupying a portion of the second upper substrate, the first well region doped with an impurity of a second conductivity type, the second conductivity type opposite to the first conductivity type, the second well region occupying a portion of the first well region, the second well region doped with the first conductivity type.

9. The non-volatile memory device of claim 1 , wherein the memory cell array includes
a plurality of gate conductive layers on the second upper substrate, and
a plurality of channel layers penetrating the plurality of gate conductive layers, the plurality of channel layers extending in a direction perpendicular to a top surface of the second upper substrate.

10. A non-volatile memory device comprising:
a lower substrate;
a peripheral region on the lower substrate, the peripheral region including a peripheral circuit on the lower substrate;
a memory cell region on the peripheral region, the memory cell region including an upper substrate, the memory cell region further including a memory cell array on the upper substrate, the upper substrate including
a first upper substrate,
a second upper substrate above the first upper substrate, and
a first layer between the first upper substrate and the second upper substrate; and

a contact, the contact extending through a portion of a lower insulation layer between the upper substrate and the lower substrate to contact a bottom surface of the first upper substrate to be electrically connected to the first upper substrate, the contact configured to transfer a voltage to the first upper substrate based on an operation signal being applied to the memory cell array.

11. The non-volatile memory device of claim 10 , wherein the upper substrate further includes
a second layer on the second upper substrate, and
a third upper substrate on the second layer.

12. The non-volatile memory device of claim 11 , wherein
the first layer includes a dielectric layer, and
the non-volatile memory device further includes a capacitor, the capacitor including the first upper substrate, the second upper substrate, and the first layer.

13. The non-volatile memory device of claim 11 , further comprising:
a separate contact, the separate contact penetrating through the second layer and the third upper substrate and extending in a direction perpendicular to a top surface of the second upper substrate,
wherein the non-volatile memory device is configured to apply a ground voltage to the second upper substrate through the separate contact based on the operation signal being applied to the memory cell array.

14. The non-volatile memory device of claim 11 , wherein
the first upper substrate, the second upper substrate, and the third upper substrate include poly-silicon doped with an impurity of a first conductivity type, and
the second layer includes poly-silicon doped with an impurity of a second conductivity type, the second conductivity type opposite to the first conductivity type.

15. The non-volatile memory device of claim 10 , wherein the non-volatile memory device is configured to apply a power supply voltage associated with the peripheral circuit to the first upper substrate based on an operation signal associated with an operation of the memory cell array being applied to the memory cell region.

16. A method of fabricating a non-volatile memory device, the method comprising:
forming one or more peripheral transistors on a portion of a lower substrate, the one or more peripheral transistors connected to a plurality of peripheral circuit wires, a lower insulation layer covering the one or more peripheral transistors and the peripheral circuit wires;
forming a first upper substrate on the lower insulation layer;
forming a first layer on the first upper substrate;
forming a second upper substrate on the first layer;
forming a memory cell region on the second upper substrate, the memory cell region including a memory cell array; and
forming a contact that extends through a portion of the lower insulation layer to contact a bottom surface of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Dong-Kil
• Kim Chan-Ho
• Kwak Pan-Suk
• Jeon Hong-Soo

Classifications

• G11C11/5621

  using charge storage in a floating gate · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L29/94

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic