Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9385137-B2
Application number	US-201213344757-A
Country	US
Kind code	B2
Filing date	Jan 6, 2012
Priority date	Jun 22, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a stacked body with an insulating film and a conductive film alternately stacked therein in a stacking direction, and a trench formed therein, the trench extending in a first direction perpendicular to the stacking direction, and the conductive film being divided by the trench;
a plurality of semiconductor pillars provided in the trench, respective lengths of the plurality of semiconductor pillars extending in the stacking direction of the insulating film and the conductive film, the plurality of semiconductor pillars being arranged along the first direction in the trench;
charge accumulation layers provided around the semiconductor pillars; and
a first insulating member provided between the charge accumulation layers in the trench,
wherein the charge accumulation layers are sandwiched between the plurality of semiconductor pillars and the conductive film, such that the charge accumulation layers abut the conductive film, and such that the sandwiched charge accumulation layers, the plurality of semiconductor pillars, and the conductive film have a positional relationship of parallel plates viewed along the first direction, and
wherein an outer edge of each of the semiconductor pillars includes a pair of circular arcs and a pair of line segments as viewed in the stacking direction.

2. The device according to claim 1 , wherein a region of a side surface of each of the semiconductor pillars opposed to a side surface of the trench constitutes a plane parallel to the side surface of the trench.

3. The device according to claim 1 , wherein
narrow width portions having a relatively narrow width and wide width portions having a relatively wide width are alternately arranged along the first direction in the trench, and
each of the semiconductor pillars is located in each of the wide width portions.

4. The device according to claim 1 , wherein the first direction is in parallel with an interface between the insulating film and the conductive film.

5. The device according to claim 1 , wherein the semiconductor pillars and the first insulating member are arranged alternately along the first direction.

6. The device according to claim 1 , wherein the conductive film is not disposed between the plurality of semiconductor pillars in the first direction within the trench.

7. The device according to claim 1 , further comprising second insulating members extending in the first direction, the second insulating members and the trench being arranged alternately along a second direction, the second direction crossing both the first direction and the stacking direction, two of divided portions of the conductive film being disposed between two of the second insulating members lying next to each other in the second direction.

Assignees

• Omura Mitsuhiro
• Toshiba Kk

Inventors

• Omura Mitsuhiro

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title