3-Dimensional semiconductor memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9595346-B2
Application number	US-201615157720-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	May 21, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device comprising:
a cell array formed on a first substrate; and
a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, the peripheral circuit being configured to provide signals for controlling the cell array,
wherein the cell array comprises:
insulating patterns and gate patterns stacked alternately on the first substrate; and
at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns,
wherein a first ground selection transistor includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor includes a second gate pattern positioned on the first gate pattern and the first pillar, and
wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

2. The three-dimensional semiconductor memory device of claim 1 , wherein the first substrate comprises a poly-crystalline silicon semiconductor.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the first pillar comprises:
a lower active pattern crossing the first gate pattern; and
an upper active pattern crossing the second gate pattern.

4. The three-dimensional semiconductor memory device of claim 3 , wherein the lower active pattern is provided in the form of a pillar and the upper active pattern is provided in the form of a tube which is filled with a filling dielectric pattern.

5. The three-dimensional semiconductor memory device of claim 1 , wherein a third gate pattern corresponding to a dummy word line and gate patterns corresponding to a plurality of word lines are formed on the second gate pattern, and
wherein a distance between the second gate pattern and the third gate pattern is wider than a cell distance between adjacent gate patterns among the plurality of word lines.

6. The three-dimensional semiconductor memory device of claim 1 , wherein a threshold voltage of the second ground selection transistor is set according to a characteristic of the first ground selection transistor.

7. The three-dimensional semiconductor memory device of claim 6 , wherein the first gate pattern is separated into a plurality of segments corresponding to a plurality of planes, and
wherein, at a program verify operation on the second ground selection transistor, the first gate pattern is activated by a stacked plane set and a verify operation is performed by the stacked plane set.

8. The three-dimensional semiconductor memory device of claim 1 , wherein the device is configured such that a level of a voltage applied to the first gate pattern is identical to that applied to the second gate pattern.

9. The three-dimensional semiconductor memory device of claim 1 , wherein the device is configured such that during a program operation on the cell array, a ground voltage is applied to a first ground selection line connected to the first gate pattern and to a second ground selection line connected to the second gate pattern.

10. The three-dimensional semiconductor memory device of claim 1 , wherein the device is configured such that during a program operation on the cell array, a first ground selection voltage higher than a ground voltage is applied to a first ground selection line connected to the first gate pattern, and the ground voltage is applied to a second ground selection line connected to the second gate pattern.

11. The three-dimensional semiconductor memory device of claim 1 , wherein the device is configured such that during a program operation on the cell array, a ground voltage is applied to a first ground selection line connected to the first gate pattern and a second ground selection voltage higher than the ground voltage is applied to a second ground selection line connected to the second gate pattern.

12. The three-dimensional semiconductor memory device of claim 1 , wherein the device is configured such that during a program operation on the cell array, a first ground selection voltage is applied to a first ground selection line connected to the first gate pattern and a second ground selection voltage higher than the first ground selection voltage is applied to a second ground selection line connected to the second gate pattern.

13. A three-dimensional semiconductor memory device comprising:
a peripheral circuit formed on a first substrate;
a second substrate at least partially overlapping the first substrate and including a poly-crystalline silicon semiconductor;
a stack structure including insulating patterns and gate patterns stacked alternately on the second substrate; and
at least a first pillar penetrating the stack structure and contacting the second substrate through conductive material and insulating materials in a direction perpendicular to the second substrate,
wherein a first ground selection transistor having a first gate insulating layer is formed to include the first pillar and a first gate pattern and is adjacent to the second substrate, and a second ground selection transistor having a second gate insulating layer is formed to include the first pillar and a second gate pattern, which is positioned on the first gate pattern, and
wherein the first ground selection transistor does not include a charge storage layer.

14. The three-dimensional semiconductor memory device of claim 13 , wherein the first pillar comprises:
a lower active pattern penetrating the first gate pattern and contacting a well area of the second substrate; and
an upper active pattern penetrating the second gate pattern and stacked on the lower active pattern.

15. The three-dimensional semiconductor memory device of claim 14 , wherein the lower active pattern comprises a poly-crystalline silicon semiconductor.

16. The three-dimensional semiconductor memory device of claim 15 , wherein a first ground selection transistor including the lower active pattern and the first gate pattern comprises a vertical channel perpendicular to the second substrate and a horizontal channel parallel to the second substrate.

17. The three-dimensional semiconductor memory device of claim 13 , wherein a third gate pattern corresponding to a dummy word line is provided on the second gate pattern, and
wherein a distance between the second gate pattern and the third gate pattern is wider than a distance between gate patterns corresponding to cells for storing data.

18. A three-dimensional semiconductor memory device comprising:
a cell array formed on a first substrate, the cell array including a plurality of vertical NAND strings,
a peripheral circuit formed on a second substrate that at least partially overlaps the first substrate, the peripheral circuit being configured to provide signals for controlling the cell array;
a connection circuit interconnection electrically connecting the cell array with the peripheral circuit;
wherein the cell array comprises:
a first gate transistor including a first gate pattern and an epitaxial layer; and
at least one second gate transistor including a second gate pattern, wherein the at least one second gate transistor is programmable.

19. The three-dimensional semiconductor memory device of claim 18 , wherein the first substrate comprises a poly-crystalline silicon semiconductor.

20. The three-dimensional semiconductor memory device of claim 18 , further co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Changhyun
• Lee Dohyun
• Park Youngwoo
• Ahn Su Jin
• Lee Jaeduk

Classifications

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11526

  Electricity · mapped topic