Stitched devices

Patent metadata

Field	Value
Publication number	US-10535645-B2
Application number	US-201715402166-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	May 18, 2015
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.

First claim

What is claimed is:

1. A stitched device comprising:
a wafer having first and second major surfaces, wherein the wafer includes
a first base device of the stitched device, wherein the first base device includes a first adjacent side, and
a second base device of the stitched device, wherein the second base device includes a second adjacent side, wherein the first and second adjacent sides are common sides of the first and second base devices;

a stitching level disposed on the first major surface of the wafer, wherein the stitching level covers the first and second base devices of the stitched device, wherein the stitching level is an interconnect level of the stitched device;
first interconnects of the first base device disposed in the stitching level, wherein the first interconnects have a first pattern which includes first stitching points located at the first adjacent side of the first base device; and
second interconnects of the second base device disposed in the stitching level, wherein the second interconnects have a second pattern which includes second stitching points located at the second adjacent side of the second base device, wherein the first and second interconnects are electrically coupled at the first and second stitching points to form stitched interconnects which electrically couple the first and second base devices.

2. The device of claim 1 wherein the stitched device comprises a stitched integrated circuit with stitched first and second base integrated circuit devices.

3. The device of claim 2 wherein the stitched device comprises additional base devices.

4. The device of claim 2 wherein the stitched device comprises a plurality of stitching levels in a plurality of interconnect levels.

5. The device of claim 2 wherein the stitching level comprises an upper interconnect level with larger design rules.

6. The device of claim 1 wherein the stitched device comprises an interposer with stitched first and second base interposers.

7. The device of claim 6 wherein the stitched interposer comprises additional base interposers.

8. The device of claim 6 wherein the stitching level comprises an interconnect level of a redistribution layer.

9. The device of claim 8 wherein the stitched device comprises a plurality of stitching levels in a plurality of interconnect levels.

10. The device of claim 1 wherein one of the first and second interconnects at the stitching point comprises a stitch coupler, wherein the stitch coupler has a larger width than a width of the interconnects.

11. The device of claim 10 wherein the first and second interconnects at the stitching point comprise stitch couplers.

12. The device of claim 10 wherein the stitching level comprises a plurality of stitching points for coupling a plurality of first interconnects to a plurality of second interconnects.

13. A stitched device comprising:
a wafer having first and second major surfaces, wherein the wafer includes
a first base device of the stitched device, wherein the first base device includes a first adjacent side, and
a second base device of the stitched device, wherein the second base device includes a second adjacent side, wherein the first and second adjacent sides are common sides of the first and second base devices;

a stitching level disposed on the first major surface of the wafer, wherein the stitching level covers the first and second base devices of the stitched device, wherein the stitching level is an interconnect level of the stitched device;
first interconnects of the first base device disposed in the stitching level, wherein the first interconnects have a first pattern which includes at least one first stitching point located at the first adjacent side of the first base device; and
second interconnects of the second base device disposed in the stitching level, wherein the second interconnects have a second pattern which includes at least one second stitching point located at the second adjacent side of the second base device, wherein the first interconnect at the at least one first stitching point is electrically coupled to the second interconnect at the at least one second stitching point.

14. The device of claim 13 wherein the stitched device comprises a plurality of stitching levels in a plurality of interconnect levels.

Assignees

• Globalfoundries Sg Pte Ltd
• Alsephina Innovations Inc

Inventors

• Shao Wei
• Tan Juan Boon
• Liu Wei
• Yi Wanbing

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title