Monolithic integrated circuit die having modular die regions stitched together

Patent metadata

Field	Value
Publication number	US-9547034-B2
Application number	US-201313935066-A
Country	US
Kind code	B2
Filing date	Jul 3, 2013
Priority date	Jul 3, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

First claim

What is claimed is:

1. An apparatus comprising:
a monolithic integrated circuit die having a plurality of modular die regions;
wherein the modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions;
wherein each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines, wherein each metal line of the plurality of metal lines continuously extends between and serially couples the adjacent pair of the modular die regions;
wherein the plurality of modular die regions includes a first die region and a second die region;
wherein the first die region includes first select circuits coupled to a first programmable termination block to receive a first select signal;
wherein the first select circuits are first multiplexers of the first die region;
wherein the second die region includes second select circuits coupled to a second programmable termination block to receive a second select signal; and
wherein the second select circuits are second multiplexers of the second die region.

2. The apparatus according to claim 1 , wherein:
the first die region has a first power distribution network of the plurality of power distribution networks;
the second die region has a second power distribution network of the plurality of power distribution networks;
the first power distribution network is separate from the second power distribution network for operation of the first die region independently from the second die region; and
the first die region and the second die region are interconnected to one another through the plurality of metal lines.

3. The apparatus according to claim 1 , wherein:
the monolithic integrated circuit die has an overall length which is a combination of a length of the first die region and a length of the second die region; and
the overall length exceeds a maximum imaging dimension for a lithographic operation.

4. The apparatus according to claim 3 , wherein a die seal of the monolithic integrated circuit die comprises:
a first wall formed in the first die region; and
a second wall formed in the second die region;
wherein the first wall and the second wall face one another and are connected to one another to provide the die seal of the monolithic integrated circuit die.

5. The apparatus according to claim 2 , wherein:
a first portion of the plurality of metal lines extend from the first die region to first input ports of the second select circuits of the second die region; and
a second portion of the plurality of metal lines extend within the second die region to second input ports of the second select circuits of the second die region.

6. The apparatus according to claim 5 , wherein:
a third portion of the plurality of metal lines extend from the second die region to first input ports of the first select circuits of the first die region; and
a fourth portion of the plurality of metal lines extend within the first die region to second input ports of the first select circuits of the first die region.

7. The apparatus according to claim 1 , wherein:
the first multiplexers are coupled to receive the first select signal for selection between a first loopback mode and a first stitch mode for the first die region; and
the second multiplexers are coupled to receive the second select signal for selection between a second loopback mode and a second stitch mode for the second die region.

8. The apparatus according to claim 6 , wherein the first portion and the third portion of the plurality of metal lines extend through a mask stitching region between the first die region and the second die region.

9. The apparatus according to claim 1 , wherein the first programmable termination block and the second programmable termination block are respectively provided with a first configuration block of the first die region and a second configuration block of the second die region.

10. An apparatus comprising:
a monolithic integrated circuit die having a plurality of modular die regions;
wherein the modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions;
wherein each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines, wherein each metal line of the plurality of metal lines continuously extends between and serially couples the adjacent pair of the modular die regions;
wherein the plurality of modular die regions includes a first die region and a second die region;
wherein the first die region includes first select circuits coupled to a first programmable termination block to receive a first select signal;
wherein the first select circuits are first multiplexers of the first die region;
wherein the second die region includes second select circuits coupled to a second programmable termination block to receive a second select signal;
wherein the second select circuits are second multiplexers of the second die region;
wherein a first portion of the plurality of metal lines extend from the first die region to first input ports of the second select circuits of the second die region; and
wherein a second portion of the plurality of metal lines extend within the second die region to second input ports of the second select circuits of the second die region.

11. The apparatus according to claim 10 , wherein:
a third portion of the plurality of metal lines extend from the second die region to first input ports of the first select circuits of the first die region; and
a fourth portion of the plurality of metal lines extend within the first die region to second input ports of the first select circuits of the first die region.

12. The apparatus according to claim 10 , wherein:
the first multiplexers are coupled to receive the first select signal for selection between a first loopback mode and a first stitch mode for the first die region; and
the second multiplexers are coupled to receive the second select signal for selection between a second loopback mode and a second stitch mode for the second die region.

13. The apparatus according to claim 11 , wherein the first portion and the third portion of the plurality of metal lines extend through a mask stitching region between the first die region and the second die region.

14. The apparatus according to claim 10 , wherein the first programmable termination block and the second programmable termination block are respectively provided with a first configuration block of the first die region and a second configuration block of the second die region.

15. The apparatus according to claim 10 , wherein the first select signal is sourced from the first programmable termination block and wherein the second select signal is sourced from the second programmable termination block.

Assignees

• Xilinx Inc

Inventors

• Camarota Rafael C

Classifications

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/318505 Primary

  Test of Modular systems, e.g. Wafers, MCM's · CPC title

• G01R31/26 Primary

  Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00}) · CPC title

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title

• H03K19/17788

  for input/output [I/O] voltages · CPC title