Display panel, electronic device and test method

Patent metadata

Field	Value
Publication number	US-10529271-B2
Application number	US-201715795210-A
Country	US
Kind code	B2
Filing date	Oct 26, 2017
Priority date	Apr 24, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Provided are a display panel, an electronic device and a test method. The display panel includes: multiple data lines extending in a first direction; a display array including multiple pixel units arranged in an array, where the columns of the pixel units are electrically connected to the data lines respectively; a test switching circuit arranged at one side of the display array and test pins and a drive pin arranged at the other side of the display array in the first direction, where the test switching circuit includes a control end, input ends and output ends, the drive pin is connected to the control end, the test pins are configured to input a test signal and are connected to the input ends via a portion of the data lines, and the remaining data lines are connected to the output ends.

First claim

The invention claimed is:

1. A display panel, comprising:
a plurality of data lines arranged in parallel and extending in a first direction;
a display array comprising a plurality of pixel units arranged in an array, wherein the number of columns of the pixel units is equal to the number of the data lines, and the columns of the pixel units are electrically connected to the data lines respectively;
a test switching circuit arranged at one side of the display array in the first direction; and
test pins and a drive pin arranged at the other side of the display array in the first direction,
wherein, the test switching circuit comprises a control end, input ends and output ends, the drive pin is electrically connected to the control end and is configured to input a switch control signal, the test pins are configured to input a test signal and are electrically connected to the input ends via a portion of the data lines, and the remaining data lines are electrically connected to the output ends.

2. The display panel according to claim 1 , wherein,
the number of the test pins is represented as m, with m being a positive integer;
the number of the data lines is represented as n, with n being a positive integer;
the test switching circuit comprises one control end, a input ends, and b output ends, with both a and b being positive integers; and
wherein, m, n, a and b meet following relational expressions: a+b≤n, a≤m and m+b=n, the test pins are electrically connected to the input ends via the portion of the data lines respectively, and the output ends are electrically connected to the remaining data lines respectively.

3. The display panel according to claim 2 , wherein, the test switching circuit comprises b first thin film transistors arranged in sequence in a second direction, the second direction is perpendicular to the first direction and is parallel to a row direction of the pixel units, and the first thin film transistors correspond to the output ends respectively; and
each of the first thin film transistors comprises a control electrode, a first electrode and a second electrode, the first electrodes of the first thin film transistors are electrically connected to the output ends corresponding to the first thin film transistors respectively, the control electrodes of all of the first thin film transistors are electrically connected to the control end, and the second electrode of each of the first thin film transistors is electrically connected to one of the input ends.

4. The display panel according to claim 3 , wherein, a=2, and two input ends are an odd input end and an even input end respectively.

5. The display panel according to claim 4 , wherein, n is an even number and n=2N, with N being a positive integer;
in the second direction, 2N data lines are divided equally into N groups, with each of the groups comprising two adjacent data lines, wherein the i-th group comprises the (2i−1)-th data line and the 2i-th data line, with i being a positive integer not greater than N;
m=2, and two test pins are an odd pin and an even pin respectively;
the odd pin is electrically connected to the odd input end via one of the data lines in an odd group of the N groups, and the remaining N−1 data lines in all of odd groups of the N groups are electrically connected to the odd input end via the output ends corresponding to the remaining N−1 data lines in all of the odd groups respectively; and
the even pin is electrically connected to the even input end via one of the data lines in an even group of the N groups, and the remaining N−1 data lines in all of even groups of the N groups are electrically connected to the even input end via the output ends corresponding to the remaining N−1 data lines in all of the even groups respectively.

6. The display panel according to claim 4 , wherein, n is an even number and n=2N, with N being a positive integer;
in the second direction, 2N data lines are divided equally into N groups, with each of the groups comprising two adjacent data lines, wherein the i-th group comprises the (2i−1)-th data line and the 2i-th data line, with i being a positive integer not greater than N;
m=4, and four test pins comprises two odd pins and two even pins;
the two odd pins are electrically connected to the odd input end via two data lines in a same odd group of the N groups respectively, and the remaining N−2 data lines in all of odd groups of the N groups are electrically connected to the odd input end via the output ends corresponding to the remaining N−2 data lines in all of the odd groups respectively; and
the two even pins are electrically connected to the even input end via two data lines in a same even group of the N groups respectively, and the remaining N−2 data lines in all of even groups of the N groups are electrically connected to the even input end via the output ends corresponding to the remaining N−2 data lines in all of the even groups respectively.

7. The display panel according to claim 4 , wherein, m=2, two test pins are an odd pin and an even pin respectively;
the odd pin is electrically connected to the odd input end via the data line electrically connected to an odd column of the pixel units, and the data lines electrically connected to the remaining odd columns of the pixel units are electrically connected to the odd input end via the output ends corresponding to the data lines electrically connected to the remaining odd columns of the pixel units respectively; and
the even pin is electrically connected to the even input end via the data line electrically connected to an even column of the pixel units, and the data lines electrically connected to the remaining even columns of the pixel units are electrically connected to the even input end via the output ends corresponding to the data lines electrically connected to the remaining even columns of the pixel units respectively.

8. The display panel according to claim 4 , wherein, m=4, and four test pins comprises two odd pins and two even pins;
one of the two odd pins is electrically connected to the odd input end via the data line electrically connected to an odd column of the pixel units, the other one of the two odd pins is electrically connected to the odd input end via the data line electrically connected to another odd column of the pixel units, and the data lines electrically connected to the remaining odd columns of the pixel units are electrically connected to the odd input end via the output ends corresponding to the data lines electrically connected to the remaining odd columns of the pixel units respectively; and
one of the two even pins is electrically connected to the even input end via the data line electrically connected to an even column of the pixel units, the other one of the two even pins is electrically connected to the even input end via the data line electrically connected to another even column of the pixel units, and the data lines electrically connected to the remaining even columns of the pixel units are electrically connected to the even input end via the output ends corresponding to the data lines electrically connected to the remaining even columns of the pixel units respectively.

9. The display panel according to claim 3 , wherein, the pixel units of the display panel have three different colors comprising a first color, a second color and a third color, the pixel units in a same column of the display array have a same color, and colors of any three sequential pixel units in a same row of the display array are different from each other; and
a=3, and three input ends comprises a first input end, a second input end and a third input end.

10. The display panel according to claim 9 , wherein, m=

Assignees

• Shanghai Tianma Am Oled Co Ltd

Inventors

• Zhou Jingxiong
• Zhou Ruiyuan

Classifications

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F1/1309

  Repairing; Testing · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• H01L27/3276

  Electricity · mapped topic