Array substrate and method for manufacturing the same, a display panel and method for testing the same, and a display apparatus

Patent metadata

Field	Value
Publication number	US-2016274387-A1
Application number	US-201514744459-A
Country	US
Kind code	A1
Filing date	Jun 19, 2015
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

There are provided an array substrate and method for manufacturing the same, a display panel and method for testing the same, and a display apparatus. The array substrate comprises a display region and at least one bond region located outside of the display region; wherein a plurality of signal lines are disposed within the display region, and a plurality of wiring terminals connected to multiple ones of the plurality of signal lines through a plurality of first lead wires are disposed within each bond region; the array substrate further comprises one or more test regions corresponding to arbitrary one or more of the at least one bond region; wherein a plurality of test terminals are disposed within each test region, and the plurality of test terminals within any one of the one or more test regions are connected with the plurality of wiring terminals within a respective one of the at least one bond region through a plurality of second lead wires. The present invention implements a lead wire open test for a display panel for which the lead wire open test cannot be implemented in a traditional test mode.

First claim

1 . An array substrate, comprising a display region and at least one bond region located outside of the display region;
wherein a plurality of signal lines are disposed within the display region, and a plurality of wiring terminals connected to multiple ones of the plurality of signal lines through a plurality of first lead wires are disposed within each bond region; the array substrate further comprises one or more test regions corresponding to arbitrary one or more of the at least one bond region; wherein a plurality of test terminals are disposed within each test region, and the plurality of test terminals within any one of the one or more test regions are connected with the plurality of wiring terminals within a respective one of the at least one bond region through a plurality of second lead wires.

2 . The array substrate of claim 1 , characterized in that the number and arrangement of the plurality of wiring terminals are identical to those of the plurality of test terminals, and the size and shape of each wiring terminal are identical to those of each test terminal.

3 . The array substrate of claim 1 , characterized in that each test region is located at a side of a respective one of the at least one bond region away from the display region.

4 . A method for manufacturing an array substrate, characterized in that, the array substrate comprises a display region and at least one bond region, and any one of the at least one bond region is located at a side of the display region;
the method comprises forming a pattern comprising the at least one bond region and one or more test regions corresponding to any one or more of the at least one bond region; wherein a plurality of signal lines are disposed within the display region, and a plurality of wiring terminals connected to multiple ones of the plurality of signal lines through a plurality of first lead wires are disposed within each bond region; and wherein a plurality of test terminals are disposed within each test region, and the plurality of test terminals within any one of the one or more test regions are connected with the plurality of wiring terminals within a respective one of the at least one bond region through a plurality of second lead wires.

5 . The method of claim 4 , characterized in that the number and arrangement of the plurality of wiring terminals are identical to those of the plurality of test terminals, and the size and shape of each wiring terminal are identical to those of each test terminal.

6 . The method of claim 4 , characterized in that each test region is located at a side of a respective one of the at least one bond region away from the display region.

7 . A display panel, characterized in that, comprising the array substrate of claims 1 .

8 . A method for testing the display panel of claim 7 , characterized in that, the method comprises:
for each test region, contacting a first test group of pins with the plurality of test terminals within the test region; providing a bias voltage to the display panel and providing a drive signal to the display panel through the first test group of pins; and observing display of the display panel to obtain a result of a lead wire open test.

9 . The method of claim 8 , characterized in that each pin of the first test group of pins has a predefined width in order to be contacted with two or more columns of test terminals.

10 . The method of claim 8 , further comprising:
disconnecting the first test group of pins with the display panel; and providing a drive signal and a bias voltage to the display panel through a shorting bar circuit to obtain a display test result for the display panel.

11 . A display apparatus, comprising the display panel of claim 7 .

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Zheng Yaoxie
• Bian Zheng
• Zhu Jinwei

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title