Ramp signal generating circuit and signal generator, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-2016013777-A1
Application number	US-201414429516-A
Country	US
Kind code	A1
Filing date	Apr 28, 2014
Priority date	Dec 19, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register ( 11 ), a second shift register ( 12 ), a voltage decreasing unit ( 13 ) and a sampling unit ( 14 ); the voltage decreasing unit ( 13 ) is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register ( 11 ) is connected to the voltage decreasing unit ( 13 ) and is configured to control the voltage decreasing unit ( 13 ) to output voltages which are decreased continuously stage by stage; the sampling unit ( 14 ) has an output terminal and is connected to the voltage decreasing unit ( 13 ); the second shift register ( 12 ) is connected to the sampling unit ( 14 ) and is configured to control the sampling unit ( 14 ) to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit ( 13 ). Such ramp signal generating circuit is capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.

First claim

1 . A ramp signal generating circuit comprising:
a first shift register, a second shift register, a voltage decreasing unit and a sampling unit; wherein the voltage decreasing unit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal, and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage; the sampling unit has an output terminal and is connected to the voltage decreasing unit; and the second shift register is connected to the sampling unit and is configured to control the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit.

2 . The ramp signal generating circuit of claim 1 , wherein the voltage decreasing unit comprises: a plurality of first transistors arranged in a matrix and a plurality of voltage decreasing resistors;
gates of the first transistors located in a same row are connected to an output terminal of the first shift register; first electrodes of the first transistors located in a same column are connected to an input terminal of the sampling unit; second electrodes of the first transistors located in a same row are connected in series and one of the voltage decreasing resistors is connected between the second electrodes of every two adjacent first transistors, except the first transistors located in last two rows, the second electrode of the first transistor located at a last column of each row is connected to the second electrode of the first transistor located at a first column of a row which is two-rows next to the row through a resistor row.

3 . The ramp signal generating circuit of claim 2 , wherein
input terminals of the first shift register are connected to a first clock signal, a second clock signal and a first frame start signal, and is configured to turn on the first transistors row by row; input terminals of the second shift register are connected to a third clock signal, a fourth clock signal and a second frame start signal, and is configured to, during an ON period of the first transistors located in a same row, control the sampling unit to sample column by column the voltage at the first electrode of each of the first transistors located in the same row.

4 . The ramp signal generating circuit of claim 2 , wherein the sampling unit comprises: a plurality of second transistors;
gates of the second transistors are connected to different output terminals of the second shift register, and first electrodes of the second transistors are connected to an output terminal of the sampling unit; a second electrode of each of the second transistors is connected to the first electrodes of the first transistors located in a same column.

5 . The ramp signal generating circuit of claim 4 , wherein
both the first transistors and the second transistors are N type transistors, or both the first transistors and the second transistors are P type transistors; when the first transistors and the second transistors are N type transistors, the first electrodes of the transistors are sources and the second electrodes of the transistors are drains.

6 . The ramp signal generating circuit of claim 2 , wherein
the first power supply input terminal is connected to the second electrode of the first transistor located at the first transistor row and the first column in the voltage decreasing unit; the second power supply input terminal is connected to the second electrode of the first transistor located at the second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the last second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the last transistor row and the last column is connected to the ground terminal; or the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the last column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the last column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the first column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the first column is connected to the ground terminal; or the first power supply input terminal is connected to the second electrode of the first transistor located at the last transistor row and the first column; the second power supply input terminal is connected to the second electrode of the first transistor located at the last second transistor row and the first column through a resistor row connected in series; the second electrode of the first transistor located at the second transistor row and the last column is connected to the ground terminal through a resistor row connected in series; and the second electrode of the first transistor located at the first transistor row and the last column is connected to the ground terminal.

7 . The ramp signal generating circuit of claim 2 , wherein
sum of resistance values of all of the voltage decreasing resistors located in each single transistor row is same and is equal to a total resistance value of each single resistor row; signal inputted from the first power supply input terminal and signal inputted from the second power supply input terminal are same.

8 . The ramp signal generating circuit of claim 1 , further comprising:
an amplifying unit having an input terminal connected to the output terminal of the sampling unit and being configured for amplifying power of the voltage outputted from the sampling unit.

9 . (canceled)

10 . An array substrate comprising a first shift register and a second shift register, wherein the first shift register is configured to generate gate line scan signals and the second shift register is configured to generate data line scan signals, the array substrate further comprising:
a voltage decreasing unit and a sampling unit, wherein the voltage decreasing unit is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal, and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage; the sampling unit has an output terminal and is connected to the voltage decreasing unit; and the second shift register is connected to the sampling unit and is configured to control the sampling unit to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit.

11 . The array substrate of claim 10 , wherein the voltage decreasing unit comprises: a plurality of first transistors arranged in a matrix and a plurality of voltage decreasing resistors;
gates of the first transistors located i

Assignees

• Boe Techology Group Co Ltd
• Beijing Boe Optoelectronics
• Boe Technology Group Co Ltd

Inventors

• Duan Liye
• Wang Lirong
• Wu Zhongyuan

Classifications

• H03K4/06 Primary

  having triangular shape · CPC title

• G09G2310/0259

  with use of an analog or digital ramp generator in the column driver or in the pixel circuit · CPC title

• G09G5/20

  Function-generator circuits, e.g. circle generators {line or curve smoothing circuits} · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title