Array substrate, its manufacturing method and testing method, and display device

Patent metadata

Field	Value
Publication number	US-2017194219-A1
Application number	US-201615235945-A
Country	US
Kind code	A1
Filing date	Aug 12, 2016
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

The present disclosure provides an array substrate, its manufacturing method and testing method, and a display device. The array substrate includes a (Test Element Group) TEG arranged at a non-display area and including a plurality of to-be-tested elements and a plurality of testing contact electrodes configured to test the to-be-tested elements. Each of the to-be-tested elements is connected to at least two of the testing contact electrodes, and at least one of the testing contact electrodes is shared by at least two of the to-be-tested elements.

First claim

What is claimed is:

1 . An array substrate, comprising a Testing Element Group (TEG) arranged at a non-display area of the array substrate, wherein the TEG comprises a plurality of to-be-tested elements and a plurality of testing contact electrodes configured to test the to-be-tested elements, each of the to-be-tested elements is connected to at least two of the testing contact electrodes, and at least one of the testing contact electrodes is shared by at least two of the to-be-tested elements.

2 . The array substrate according to claim 1 , wherein the to-be-tested elements comprises a first Thin Film Transistor (TFT) and a second TFT, a gate electrode, a source electrode and a drain electrode of each of the first and second TFTs are connected to the testing contact electrodes respectively, and at least one of the testing contact electrodes is shared by the first TFT and the second TFT.

3 . The array substrate according to claim 2 , wherein a first testing contact electrode is shared by the gate electrodes of the first and second TFTs.

4 . The array substrate according to claim 3 , wherein all of the first testing contact electrode, the gate electrodes of the first and second TFTs are arranged at a same layer, and made of a same material.

5 . The array substrate according to claim 2 , wherein a second testing contact electrode is shared by one of the source electrode and the drain electrode of the first TFT and one of the source electrode and the drain electrode of the second TFT.

6 . The array substrate according to claim 5 , wherein both the second testing contact electrode and an indium tin oxide (ITO) electrode of the array substrate are arranged at a same layer, and made of a same material.

7 . The array substrate according to claim 1 , wherein the to-be-tested elements comprise a gate metal line and a gate metal layer-ITO electrode contact resistor, and a third testing contact electrode is shared by the gate metal line and the gate metal layer-ITO electrode contact resistor.

8 . The array substrate according to claim 7 , wherein both the third testing contact electrode and the gate metal line are arranged at a same layer, and made of a same material.

9 . The array substrate according to claim 1 , wherein the to-be-tested elements comprise a source-drain (SD) metal line and an SD metal layer-ITO electrode contact resistor, and a fourth testing contact electrode is shared by the SD metal line and the SD metal layer-ITO electrode contact resistor.

10 . The array substrate according to claim 9 , wherein both the fourth testing contact electrode and the SD metal line are arranged at a same layer, and made of a same material.

11 . The array substrate according to claim 1 , wherein the to-be-tested elements comprise a gate metal layer-ITO electrode contact resistor and an SD metal layer-ITO electrode contact resistor, and a fifth testing contact electrode is shared by the gate metal layer-ITO electrode contact resistor and the SD metal layer-ITO electrode contact resistor.

12 . The array substrate according to claim 11 , wherein both the fifth testing contact electrode and the ITO electrode of the array substrate are arranged at a same layer, and made of a same material.

13 . The array substrate according to claim 1 , wherein the to-be-tested elements comprise a first TFT, a second TFT, a gate metal line, an SD metal line, a gate metal layer-ITO electrode contact resistor and an SD metal layer-ITO electrode contact resistor, and nine testing contact electrodes are used by the to-be-tested elements;
a first testing contact electrode is shared by a gate electrode of the first TFT and a gate electrode of the second TFT, a second testing contact electrode is shared by a source electrode of the first TFT and a source electrode of the second TFT, a third testing contact electrode is shared by the gate metal line and the gate metal layer-ITO electrode contact resistor, a fourth testing contact electrode is shared by the SD metal line and SD metal layer-ITO electrode contact resistor, and a fifth testing contact electrode is shared by the gate metal layer-ITO electrode contact resistor and the SD metal layer-ITO electrode contact resistor; the gate electrode of the first TFT is connected to the first testing contact electrode, the source electrode of the first TFT is connected to the second testing contact electrode, and a drain electrode of the first TFT is connected to a sixth testing contact electrode; the gate electrode of the second TFT is connected to the first testing contact electrode, the source electrode of the second TFT is connected to the second testing contact electrode, and a drain electrode of the second TFT is connected to a seventh testing contact electrode; one end of the gate metal line is connected to the fourth testing contact electrode, and the other end of the gate metal line is connected to an eighth testing contact electrode; one end of the SD metal line is connected to the third testing contact electrode, and the other end of the SD metal line is connected to a ninth testing contact electrode; and the gate metal layer-ITO electrode contact resistor is connected to the fifth testing contact electrode and the fourth testing contact electrode, and the SD metal layer-ITO electrode contact resistor is connected to the fifth testing contact electrode and the third testing contact electrode.

14 . The array substrate according to claim 1 , wherein the TEG comprises M testing contact electrodes arranged in an N*N array with a row interval being identical to a column interval, wherein M=N*N, and M and N are both positive integers.

15 . A display device, comprising the array substrate according to claim 1 .

16 . A method for manufacturing the array substrate according to claim 1 .

17 . The method according to claim 16 , comprising steps of:
providing a base substrate; forming a pattern of a gate metal layer on the base substrate, the pattern of the gate metal layer including patterns of a gate electrode of a first TFT, a gate electrode of a second TFT, a gate metal line and three testing contact electrodes for the gate metal layer; forming a gate insulation layer; forming a pattern of a semiconductor layer; forming a pattern of a source-drain (SD) metal layer, the pattern of the SD metal layer including patterns of a drain electrode of the first TFT, a drain electrode of the second TFT, an SD metal line, and four testing contact electrodes for the SD metal layer; forming a passivation layer and via-holes in the passivation layer; and forming a pattern of an ITO electrode layer, the pattern of the ITO electrode layer including patterns of a source electrode of the first TFT, a source electrode of the second TFT, and two testing contact electrodes for the ITO electrode layer, one end of one of the testing contact electrodes for the ITO electrode layer being connected to one of the testing contact electrodes for the gate metal layer through one of the via-holes in the passivation layer, the other end of the one of the testing contact electrodes for the ITO electrode layer being connected to one of the testing contact electrodes for the SD metal layer through another one of the via-holes in the passivation layer, and two ends of the other one of the testing contact electrodes for the ITO electrode layer being connected to the source electrode of the first TFT and the source electrode of the second TFT respectively.

18 . A method for testing the array substrate according to claim 1 .

19 . The metho

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Ji Yu
• Wu Chengye
• Wu Zhengyun
• Feng Lei
• Wang Bei
• Song Lei

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G09G3/006

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• H01L22/14 Primary

  Electricity · mapped topic