Carrier and integrated memory

Patent metadata

Field	Value
Publication number	US-10515929-B2
Application number	US-201815948023-A
Country	US
Kind code	B2
Filing date	Apr 9, 2018
Priority date	Apr 9, 2018
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

First claim

What is claimed is:

1. A method of integrated circuit (IC) carrier fabrication comprising:
joining a memory and an IC chip carrier with a dielectric material so that a contact surface of the memory and a top surface of the dielectric material are coplanar with a top surface of the carrier;
forming a vertical interconnect access (VIA) within the dielectric material from the top surface of the dielectric material to bottom surface of the dielectric material;
forming a first carrier interconnect directly upon the contact surface of the memory, directly upon the top surface of the dielectric material, and directly upon the top surface of the carrier, the first carrier interconnect electrically connecting a signal contact of the memory and a wiring line within the IC chip carrier; and
forming a second carrier interconnect directly upon the top surface of the dielectric material, the second carrier interconnect electrically connecting a power or ground contact of the memory and the VIA.

2. The method of claim 1 , further comprising:
forming a third carrier interconnect upon the bottom surface of the dielectric material, wherein the third carrier interconnect is electrically connected to the VIA.

3. The method of claim 1 , further comprising:
subsequent to joining the memory with the IC chip carrier, joining an IC chip contact of an IC chip to the first carrier interconnect.

4. The method of claim 2 , further comprising:
joining a system board contact to the third carrier interconnect.

5. The method of claim 1 , wherein data may be read or written from the memory by an access signal received by the signal contact of the memory.

6. The method of claim 3 , wherein the contact surface of the memory faces the IC chip.

7. The method of claim 1 , further comprising:
positioning a heat spreader upon the memory and wherein the dielectric material joins the heat spreader with the memory and the IC chip carrier.

8. An integrated circuit (IC) carrier and memory package comprising:
a memory joined to a carrier by a dielectric material such that a contact surface of the memory is coplanar with a top surface of the dielectric material and coplanar with a top surface of the carrier;
a vertical interconnect access (VIA) through the dielectric material;
a first carrier interconnect directly upon the contact surface of the memory, directly upon the top surface of the dielectric material, and directly upon the top surface of the carrier, wherein the first carrier interconnect electrically connects a signal contact of the memory and a wiring line within the IC chip carrier; and
a second carrier interconnect directly upon top surface of the dielectric material, wherein the second carrier interconnect electrically connects a power or ground contact of the memory and the VIA.

9. The package of claim 8 , further comprising:
a third carrier interconnect upon a bottom surface of the dielectric material, wherein the third carrier interconnect is electrically connected to the VIA.

10. The package of claim 8 , wherein data may be read or written from the memory by an access signal received by the signal contact of the memory.

11. The package of claim 8 , further comprising a heat spreader upon the memory and wherein the dielectric material joins the heat spreader with the memory and the IC chip carrier.

12. The package of claim 8 , wherein a coefficient of thermal expansion of the dielectric material matches a coefficient of thermal expansion of the carrier.

13. The package of claim 11 , further comprising a thermal interface material between the memory and the heat spreader.

14. The package of claim 11 , wherein the heat spreader stiffens the carrier and reduces carrier warpage.

15. An electronic system comprising:
an integrated circuit (IC) carrier and memory joined by a dielectric material such that a contact surface of the memory and an IC chip facing surface of the dielectric material are coplanar with an IC chip facing surface of the carrier;
a vertical interconnect access (VIA) within the dielectric material from the IC chip facing surface of the dielectric material to a system facing surface of the dielectric material;
a first carrier interconnect directly upon the contact surface of the memory, directly upon the IC chip facing surface of the dielectric material, and directly upon the IC chip facing surface of the carrier, the first carrier interconnect electrically connecting a signal contact of the memory and a wiring line within the IC chip carrier;
a second carrier interconnect directly upon the IC chip facing surface of the dielectric material, the second carrier interconnect electrically connecting a power or ground contact of the memory and the VIA;
a third carrier interconnect directly upon the system facing surface of the dielectric material, the third carrier interconnect being electrically connected to the VIA;
an IC chip comprising an IC chip contact electrically connected to the first carrier interconnect; and
a system board comprising a system board contact electrically connected to the third carrier interconnect.

16. The system of claim 15 , wherein data may be read or written from the memory by an access signal received by the signal contact of the memory.

17. The system of claim 15 , wherein the contact surface of the memory faces the IC chip.

18. The system of claim 15 , wherein the IC chip writes data to the memory by sending data to the memory by way of the IC chip contact.

19. The system of claim 15 , wherein the IC chip reads data from the memory by receiving data from the memory by way of the IC chip contact.

20. The system of claim 15 , wherein the system board powers the memory by supplying power potential to the system board contact.

Assignees

• IBM

Inventors

• Arvin Charles L
• Erwin Brian M
• Kapfhammer Mark W
• Quinlan Brian W
• Reynolds Charles L
• Weiss Thomas

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title