BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility

Patent metadata

Field	Value
Publication number	US-9691728-B2
Application number	US-201514629350-A
Country	US
Kind code	B2
Filing date	Feb 23, 2015
Priority date	Dec 31, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.

First claim

The invention claimed is:

1. A method comprising:
forming a first portion of a build-up carrier adjacent a second side of a die, the die comprising a first side opposite the second side, wherein the second side of the die comprises a device side with contact points and comprising conductive pillars on the contact points, wherein the first portion of the build-up carrier comprises a plurality of alternating layers of conductive material and dielectric material, wherein at least one of the layers of conductive material is directly coupled to one of the conductive pillars on the contact points of the die;
forming a second portion of the build-up carrier adjacent the first side of the die, the second portion comprising at least one layer of conductive material and a plurality of contacts,
wherein forming the second portion of the build-up carrier precedes forming the first portion of the build-up carrier,
wherein forming the second portion of the build-up carrier comprises:
forming the plurality of contacts on a sacrificial substrate having a planar surface;
forming a layer of dielectric material on the plurality of contacts;
forming the at least one layer of conductive material on the layer of dielectric material so that the dielectric material is between the plurality of contacts and the at least one layer of conductive material; and
after forming the at least one layer of conductive material of the second portion of the build-up carrier, positioning the die on the at least one layer of conductive material of the second portion of the build-up carrier,

wherein forming the first portion of the build-up carrier comprises introducing a layer of dielectric material on the die and, after introducing the layer of dielectric material, patterning conductive vias through the dielectric material to the contact points of the die and a layer of conductive material on the dielectric material,
wherein the at least one layer of conductive material of the second portion is coupled to at least one of the alternating layers of conductive material on the first portion of the carrier, and
after forming the first portion of the build-up carrier, removing the sacrificial substrate to define the plurality of contact points of the second portion of the build-up carrier as accessible contact points.

2. The method of claim 1 , wherein forming the second portion of the build-up carrier comprises separating the at least one layer of conductive material on the first side of the die from the die by a dielectric material.

3. The method of claim 1 , further comprising electrically coupling the at least one layer of conductive material on the first side comprises coupling to at least one of the plurality of layers of conductive material on the second side.

4. The method of claim 1 , coupling ones of the contact points of the die to the at least one layer of conductive material of the second portion of the build-up carrier.

5. The method of claim 4 , wherein the contact points of the die that are coupled to the at least one layer of conductive material are coupled to conductive vias from the second side of the die to the first side.

Assignees

• Intel Corp

Inventors

• Nickerson Robert M
• Tao Min
• Guzek John S

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/0198

  batch processes · CPC title