Electronic device with redistribution layer and stiffeners and related methods

Patent metadata

Field	Value
Publication number	US-9698105-B2
Application number	US-201615251209-A
Country	US
Kind code	B2
Filing date	Aug 30, 2016
Priority date	Oct 11, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A method includes forming a molded panel that includes a number of integrated circuits, fan-out components and stiffeners embedded in an encapsulation material. A redistribution layer is formed over the integrated circuits and the fan-out components. The redistribution layer is electrically coupled to contacts of the integrated circuits. The molded panel is singulated to form electronic devices. Each electronic device each an integrated circuit that is separated from a fan-out component by a portion of the encapsulation material and a stiffener separated from the fan-out component by a second portion of the encapsulation material.

First claim

What is claimed is:

1. A method of making an electronic device, the method comprising:
providing an integrated circuit having a plurality of electrically conductive connectors coupled to a first surface of the integrated circuit;
forming an encapsulation material surrounding the integrated circuit and the plurality of electrically conductive connectors;
positioning a fan-out component adjacent the integrated circuit and separated therefrom by a portion of the encapsulation material;
positioning a stiffener adjacent the fan-out component and separated therefrom by a second portion of the encapsulation material;
electrically connecting a redistribution layer to the plurality of electrically conductive connectors; and
positioning a heat sink adjacent a second surface of the integrated circuit, the second surface opposite the first surface, wherein the fan-out component and the stiffener extend vertically from the heat sink to the redistribution layer.

2. The method of claim 1 , wherein the heat sink comprises a heat sink layer and a thermal interface layer between the heat sink layer and the integrated circuit.

3. The method of claim 1 , further comprising electrically coupling a plurality of electrically conductive solder balls to the redistribution layer.

4. The method of claim 1 , wherein the stiffener has an inner surface adjacent the encapsulation material and an outer surface defining an external surface of the electronic device.

5. The method of claim 1 , wherein the plurality of electrically conductive connectors comprises solder bumps or pillars.

6. A method of making an electronic device, the method comprising:
providing an integrated circuit having a plurality of electrically conductive connectors coupled to a first surface of the integrated circuit;
forming an encapsulation material surrounding the integrated circuit and the plurality of electrically conductive connectors;
positioning a fan-out component adjacent the integrated circuit and separated therefrom by a portion of the encapsulation material, wherein the fan-out component comprises an organic material or a ceramic material;
positioning a stiffener adjacent the fan-out component and separated therefrom by a second portion of the encapsulation material;
electrically connecting a redistribution layer to the plurality of electrically conductive connectors; and
positioning a heat sink layer adjacent a second surface of the integrated circuit, the second surface opposite the first surface.

7. The method of claim 6 , wherein the fan-out component comprises an organic material.

8. The method of claim 6 , wherein the fan-out component a ceramic material.

9. A method comprising:
forming a molded panel that includes a plurality of integrated circuits, a plurality of fan-out components and a plurality of stiffeners embedded in an encapsulation material;
forming a redistribution layer over the integrated circuits and the fan-out components, the redistribution layer being electrically coupled to contacts of the integrated circuits; and
singulating the molded panel to form a plurality of electronic devices, each electronic device comprising an integrated circuit that is separated from a fan-out component by a portion of the encapsulation material and a stiffener separated from the fan-out component by a second portion of the encapsulation material.

10. The method of claim 9 , further comprising forming a heat sink layer adjacent the integrated circuit of each of the plurality of electronic devices.

11. The method of claim 10 , further comprising forming a thermal interface layer between the heat sink layer and the integrated circuit.

12. The method of claim 9 , further comprising attaching a plurality of electrically conductive solder balls to the redistribution layer.

13. The method of claim 9 , wherein the fan-out components each comprise a ceramic material.

14. The method of claim 9 , wherein the fan-out components each comprise an organic material.

15. The method of claim 9 , wherein the redistribution layer comprises a dielectric layer and a plurality of electrically conductive traces carried by the dielectric layer, the electrically conductive traces being electrically coupled to contacts of the integrated circuits.

16. The method of claim 9 , wherein, for each electronic device, the stiffener has an inner surface adjacent the encapsulation material and an outer surface defining an external surface of the electronic device.

17. A method comprising:
adhering a plurality of integrated circuits, a plurality of fan-out components and a plurality of stiffeners to a carrier, the fan-out components each comprising a ceramic or organic material;
forming an encapsulation material over the carrier and between the integrated circuits, fan-out components and stiffeners;
forming a redistribution layer over the integrated circuits and the fan-out components;
forming a plurality of electrically conductive solder balls adjacent the redistribution layer, the solder balls being electrically coupled to contacts of the integrated circuits through the redistribution layer; and
performing a singulation step to form a plurality of electronic devices.

18. The method of claim 17 , wherein the singulation step comprises sawing through the encapsulation material and dissolving an adhesive layer to release the electronic devices.

19. The method of claim 17 , further comprising attaching a heat sink layer to each of the electronic devices.

20. The method of claim 17 , further comprising performing a grinding step to remove excess encapsulation material from a lower surface of each integrated circuit, then attaching the lower surface of each integrated circuit to a temporary carrier, and then forming the redistribution layer.

21. The method of claim 17 , wherein the adhering step comprises using a pick in place machine to place the integrated circuits, the fan-out components, and the stiffeners to an adhesive that overlies the carrier.

Assignees

• St Microelectronics Pte Ltd

Inventors

• Luan Jing-En

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title